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PDF FM24V05 Data sheet ( Hoja de datos )
| Número de pieza | FM24V05 | |
| Descripción | 512-Kbit (64 K x 8) Serial (I2C) F-RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FM24V05
512-Kbit (64 K × 8) Serial (I2C) F-RAM
512-Kbit (64 K × 8) Serial (I2C) F-RAM
Features
■ 512-Kbit ferroelectric random access memory (F-RAM)
logically organized as 64 K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Fast 2-wire Serial interface (I2C)
❐ Up to 3.4-MHz frequency
❐ Direct hardware replacement for serial (I2C) EEPROM
❐ Supports legacy timings for 100 kHz and 400 kHz
■ Device ID
❐ Manufacturer ID and Product ID
■ Low power consumption
❐ 175 A active current at 100 kHz
❐ 90 A (typ) standby current
❐ 5 A (typ) sleep mode current
■ Low-voltage operation: VDD = 2.0 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ 8-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM24V05 is a 512-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24V05 performs write operations at bus
speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24V05 is
capable of supporting 1014 read/write cycles, or 100 million times
more write cycles than EEPROM.
These capabilities make the FM24V05 ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24V05 provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The device
incorporates a read-only Device ID that allows the host to
determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
industrial temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
Counter
Address
Latch
16
64 K x 8
F-RAM Array
8
SDA
SCL
WP
A2-A0
Serial to Parallel
Converter
Control Logic
Data Latch
8
8
Device ID and
Manufacturer ID
Errata: STOP condition is optional for sleep mode entry. For more information, see Errata on page 18. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84462 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 6, 2015
1 page  
FM24V05
full pagewidth
SDA
Figure 3. START and STOP Conditions
SDA
SCL
S
START Condition
P
STOP Condition
SCL
handbook, full pagewidth
SDA
MSB
Figure 4. Data Transfer on the I2C Bus
Acknowledgement
signal from slave
P
Acknowledgement S
signal from receiver
SCL
S
1
START
condition
2
789
ACK
Byte complete
1
2 3 4-8
9
ACK
S
or
P
STOP or
START
condition
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
Acknowledge / No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, the receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24V05 will continue to place data onto the bus
as long as the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is needed, the
receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24V05 to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
No Acknowledge
Acknowledge
SCL FROM
MASTER
S
START
Condition
1
2
89
Clock pulse for
acknowledgement
Document Number: 001-84462 Rev. *H
Page 5 of 21
5 Page 
FM24V05
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in High-Z state .................................... –0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VDD + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount lead soldering
temperature (10 seconds) ....................................... +260 C
Electrostatic Discharge Voltage
Human Body Model (AEC-Q100-002 Rev. E) .................. 2.5 kV
Charged Device Model (AEC-Q100-011 Rev. B) ............. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ............................ 200 V
Latch-up current .................................................... > 140 mA
* Exception: The “VIN < VDD + 1.0 V” restriction does not apply
to the SCL and SDA inputs.
Operating Range
Range Ambient Temperature (TA)
VDD
Industrial
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VDD Power supply
IDD Average VDD current
ISB
IZZ
ILI
ILO
VIH
VIL
VOL1
VOL2
Rin[2]
Standby current
Sleep mode current
Input leakage current
(Except WP and A2-A0)
Input leakage current
(for WP and A2-A0)
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Output LOW voltage
Input resistance (WP, A2-A0)
Test Conditions
SCL toggling
fSCL = 100 kHz
between
VDD – 0.2 V and VSS,
other inputs VSS or
fSCL = 1 MHz
fSCL = 3.4 MHz
VDD – 0.2 V.
SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
VSS < VIN < VDD
Min
2.0
–
–
–
–
–
–1
VSS < VIN < VDD
–1
VSS < VIN < VDD
IOL = 2 mA, VDD > 2.7 V
IOL = 150 A
For VIN = VIL (Max)
For VIN = VIH (Min)
–1
0.7 × VDD
– 0.3
–
–
50
1
Typ [1]
3.3
–
–
–
90
5
–
–
–
–
–
–
–
–
–
Max
3.6
175
400
1000
Unit
V
A
A
A
150 A
8 A
+1 A
+100
A
+1
VDD + 0.3
0.3 × VDD
0.4
0.2
–
–
A
V
V
V
V
k
M
Notes
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
2. The input pull-down circuit is strong (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
Document Number: 001-84462 Rev. *H
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet FM24V05.PDF ] | |
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