FM18W08 Datasheet PDF - Cypress Semiconductor
| Part Number | FM18W08 | |
| Description | 256-Kbit (32 K x 8) Wide Voltage Bytewide F-RAM Memory | |
| Manufacturers | Cypress Semiconductor | |
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FM18W08
256-Kbit (32 K × 8) Wide Voltage Bytewide
F-RAM Memory
256-Kbit (32 K × 8) Wide Voltage Bytewide F-RAM Memory
Features
■ 256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32 K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ SRAM and EEPROM compatible
❐ Industry-standard 32 K × 8 SRAM and EEPROM pinout
❐ 70-ns access time, 130-ns cycle time
■ Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
❐ Resistant to negative voltage undershoots
■ Low power consumption
❐ Active current 12 mA (max)
❐ Standby current 20 A (typ)
■ Wide voltage operation: VDD = 2.7 V to 5.5 V
■ Industrial temperature: –40 C to +85 C
■ 28-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM18W08 is a 32 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM18W08 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM18W08 ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
A14-0
A14-0
32 K x 8
F-RAM Array
CE
Control
WE Logic
OE
I/O Latch & Bus Driver
DQ 7-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86207 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 4, 2015
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FM18W08
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 1014 cycles will allow
150,000 accesses per second to the same row for over 20 years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
falling edge of CE, users cannot ground it as they might with
SRAM.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in Figure 2 below. Also shown is a common SRAM signal
relationship that will not work for the FM18W08.
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
Figure 2. Chip Enable and Memory Address Relationships
Valid Strobing of CE
F-RAM
Signaling
CE
Address
A1
A2
Data
D1
D2
SRAM
Signaling
CE
Address
Invalid Strobing of CE
A1 A2
Data
A second design consideration relates to the level of VDD during
operation. Battery-backed SRAMs are forced to monitor VDD in
order to switch to battery backup. They typically block user
access below a certain VDD level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
F-RAM memories do not need this system overhead. The
memory will not block access at any VDD level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when VDD is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track VDD during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below VDD min. (2.7 V).
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
D1 D2
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 3. Use of Pull-up Resistor on CE
VDD
FM18W08
CE
MCU / MPU
WE
OE
A 14-0
DQ 7-0
Document Number: 001-86207 Rev. *E
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FM18W08 electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FM18W08.PDF Datasheet ] | |
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Featured Datasheets
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