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PDF FM33256B Data sheet ( Hoja de datos )
| Número de pieza | FM33256B | |
| Descripción | 256-Kbit (32 K x 8) Integrated Processor Companion | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FM33256B
256-Kbit (32 K × 8) Integrated Processor
Companion with F-RAM
256-Kbit (32 K × 8) Serial (SPI) F-RAM
Features
■ 256-Kbit ferroelectric random access memory (F-RAM)
❐ Logically organized as 32 K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ High Integration Device Replaces Multiple Parts
❐ Serial nonvolatile memory
❐ Real time clock (RTC) with alarm
❐ Low VDD detection drives reset
❐ Watchdog window timer
❐ Early power-fail warning / NMI
❐ 16-bit nonvolatile event counter
❐ Serial number with write-lock for security
■ Real-time Clock/Calendar
❐ Backup current at 2 V: 1.15 μA at +25 °C
❐ Seconds through centuries in BCD format
❐ Tracks leap years through 2099
❐ Uses standard 32.768 kHz crystal (6 pF/12.5 pF)
❐ Software calibration
❐ Supports battery or capacitor backup
■ Processor Companion
❐ Active-low reset output for VDD and watchdog
❐ Programmable low-VDD reset thresholds
❐ Manual reset filtered and debounced
❐ Programmable watchdog window timer
❐ Nonvolatile event counter tracks system intrusions or other
events
❐ Comparator for power-fail interrupt or other use
❐ 64-bit programmable serial number with lock
■ Fast serial peripheral interface (SPI)
❐ Up to 16-MHz frequency
❐ RTC, Supervisor controlled via SPI interface
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■ Low power consumption
❐ 1.1 mA active current at 1 MHz
❐ 150 μA standby current
■ Operating voltage: VDD = 2.7 V to 3.6 V
■ Industrial temperature: –40 °C to +85 °C
■ 14-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
■ Underwriters laboratory (UL) recognized
Functional Overview
The FM33256B device integrates F-RAM memory with the most
commonly needed functions for processor-based systems.
Major features include nonvolatile memory, real time clock,
low-VDD reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI) interrupt or
any other purpose.
The FM33256B is a 256-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by other nonvolatile memories. The
FM33256B is capable of supporting 1014 read/write cycles, or
100 million times more write cycles than EEPROM.
The real time clock (RTC) provides time and date information in
BCD format. It can be permanently powered from an external
backup voltage source, either a battery or a capacitor. The
timekeeper uses a common external 32.768 kHz crystal and
provides a calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed CPU
support functions. Supervisory functions include a reset output
signal controlled by either a low VDD condition or a watchdog
timeout. RST goes active when VDD drops below a
programmable threshold and remains active for 100 ms (max.)
after VDD rises above the trip point. A programmable watchdog
timer runs from 60 ms to 1.8 seconds. The timer may also be
programmed for a delayed start, which functions as a window
timer. The watchdog timer is optional, but if enabled it will assert
the reset signal for 100 ms if not restarted by the host within the
time window. A flag-bit indicates the source of the reset.
A comparator on PFI compares an external input pin to the
onboard 1.5 V reference. This is useful for generating a
power-fail interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial number that
can be locked making it unalterable. Additionally it offers an
event counter that tracks the number of rising or falling edges
detected on a dedicated input pin. The counter can be
programmed to be nonvolatile under VDD power or
battery-backed using only VBAK. If VBAK is connected to a battery
or capacitor, then events will be counted even in the absence of
VDD.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86213 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 5, 2015
1 page  
FM33256B
Overview
The FM33256B device combines a serial nonvolatile RAM with
a real time clock (RTC) and a processor companion. The
companion is a highly integrated peripheral including a
processor supervisor, analog comparator, a nonvolatile counter,
and a serial number. The FM33256B integrates these
complementary but distinct functions under a common interface
in a single package. The product is organized as two logical
devices. The first is a memory and the second is the companion
which includes all the remaining functions. From the system
perspective they appear to be two separate devices with unique
opcodes on the serial bus.
The memory is organized as a standalone nonvolatile SPI
memory using standard opcodes. The real time clock and
supervisor functions are accessed under their own opcodes. The
clock and supervisor functions are controlled by 30 special
function registers. The RTC alarm and some control registers are
maintained by the power source on the VBAK pin, allowing them
to operate from battery or backup capacitor power when VDD
drops below a set threshold. Each functional block is described
below.
Memory Architecture
The FM33256B is available with 256-Kbit of memory. The device
uses two-byte addressing for the memory portion of the chip.
This makes the device software compatible with its standalone
memory counterparts, such as the FM25W256.
The memory array is logically organized as 32,768 × 8 bits and
is accessed using an industry-standard serial peripheral
interface (SPI) bus. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the SPI bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The SPI protocol is described
on page 23.
The memory array can be write-protected by software. Two bits
(BP1, BP0) in the Status Register control the protection setting.
Based on the setting, the protected addresses cannot be written.
The Status Register & Write Protection is described in more
detail on page 26.
Processor Companion
In addition to nonvolatile RAM, the FM33256B incorporates a
real time clock with alarm and highly integrated processor
companion. The companion includes a low-VDD reset, a
programmable watchdog timer, a 16-bit nonvolatile event
counter, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic functions:
Detection of power supply fault conditions and a watchdog timer
to escape a software lockup condition. The FM33256B has a
reset pin (RST) to drive a processor reset input during power
faults, power-up, and software lockups. It is an open drain output
with a weak internal pull-up to VDD. This allows other reset
sources to be wire-OR'd to the RST pin. When VDD is above the
programmed trip point, RST output is pulled weakly to VDD. If
VDD drops below the reset trip point voltage level (VTP), the RST
pin will be driven LOW. It will remain LOW until VDD falls too low
for circuit operation which is the VRST level. When VDD rises
again above VTP, RST continues to drive LOW for at least 30 ms
(tRPU) to ensure a robust system reset at a reliable VDD level.
After tRPU has been met, the RST pin will return to the weak
HIGH state. While RST is asserted, serial bus activity is locked
out even if a transaction occurred as VDD dropped below VTP. A
memory operation started while VDD is above VTP will be
completed internally.
Table 1 below shows how bits VTP(1:0) control the trip point of
the low-VDD reset. They are located in register 18h, bits 1 and 0.
The reset pin will drive LOW when VDD is below the selected VTP
voltage, and the SPI interface and F-RAM array will be locked
out. Figure 2 illustrates the reset operation in response to a low
VDD.
Table 1. VTP setting
VTP Setting
2.6 V
2.75 V
2.9 V
3.0 V
VTP1
0
0
1
1
VTP0
0
1
0
1
Figure 2. Low VDD Reset
VDD
VTP
tRPU
RST
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 60 ms to 1.8
seconds in 60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
Figure 3. Watchdog Timer
Tim ebas e
100 ms
clock
WR(3:0) = 1010b to restart
Down Counter
RST
Watchdog
Timer Settings
WDE
Document Number: 001-86213 Rev. *C
Page 5 of 39
5 Page 
FM33256B
Table 4. Digital Calibration Adjustments
Positive Calibration for slow clocks: Calibration will achieve ± 2.17 PPM after calibration
Measured Frequency Range
Error Range (PPM)
Min Max Min Max Program Calibration Register to:
0 512.0000
1 511.9989
2 511.9967
3 511.9944
4 511.9922
511.9989
511.9967
511.9944
511.9922
511.9900
0
2.18
6.52
10.86
15.20
2.17
6.51
10.85
15.19
19.53
000000
100001
100010
100011
100100
5 511.9900
6 511.9878
7 511.9856
8 511.9833
9 511.9811
10 511.9789
11 511.9767
12 511.9744
13 511.9722
14 511.9700
15 511.9678
16 511.9656
17 511.9633
18 511.9611
19 511.9589
511.9878
511.9856
511.9833
511.9811
511.9789
511.9767
511.9744
511.9722
511.9700
511.9678
511.9656
511.9633
511.9611
511.9589
511.9567
19.54
23.88
28.22
32.56
36.90
41.24
45.58
49.92
54.26
58.60
62.94
67.28
71.62
75.96
80.30
23.87
28.21
32.55
36.89
41.23
45.57
49.91
54.25
58.59
62.93
67.27
71.61
75.95
80.29
84.63
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
20 511.9567
21 511.9544
22 511.9522
23 511.9500
24 511.9478
25 511.9456
26 511.9433
27 511.9411
28 511.9389
29 511.9367
30 511.9344
31 511.9322
511.9544
511.9522
511.9500
511.9478
511.9456
511.9433
511.9411
511.9389
511.9367
511.9344
511.9322
511.9300
84.64
88.98
93.32
97.66
102.00
106.34
110.68
115.02
119.36
123.70
128.04
132.38
88.97
93.31
97.65
101.99
106.33
110.67
115.01
119.35
123.69
128.03
132.37
136.71
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Document Number: 001-86213 Rev. *C
Page 11 of 39
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FM33256B.PDF ] | |
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