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PDF ADG528A Data sheet ( Hoja de datos )

Número de pieza ADG528A
Descripción CMOS Latched 4-/8-Channel Analog Multiplexers
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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CMOS Latched
4-/8-Channel Analog Multiplexers
ADG528A/ADG529A
FEATURES
44 V Supply Maximum Rating
VSS to VDD Analog Signal Range
Single-/Dual-Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns WR Pulse)
Extended Plastic Temperature Range
(–40°C to +85°C)
Low Leakage (20 pA typ)
Low Power Dissipation (28 mW max)
Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages
Superior Alternative to:
DG528
DG529
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG528A and ADG529A are CMOS monolithic analog
multiplexers with eight channels and four dual channels, respec-
tively. On-chip latches facilitate microprocessor interfacing. The
ADG528A switches one of eight inputs to a common output,
depending on the state of three binary addresses and an enable
input. The ADG529A switches one of four differential inputs to
a common differential output, depending on the state of two
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
The ADG528A and ADG529A are designed on an enhanced
LC2MOS process, which gives an increased signal capability of
VSS to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These multiplex-
ers also feature high switching and low RON.
PRODUCT HIGHLIGHTS
1. Single-/dual-supply specifications with a wide tolerance.
The devices are specified in the 10.8 V to 16.5 V range for
both single- and dual-supplies.
2. Easily Interfaced
The ADG528A and ADG529A can be easily interfaced with
microprocessors. The WR signal latches the state of the
address control lines and the enable line. The RS signal
clears both the address and enable data in the latches result-
ing in no output (all switches off). RS can be tied to the
microprocessor reset pin.
3. Extended Signal Range
The enhanced LC2MOS processing results in a high breakdown
and an increased analog signal range of VSS to VDD.
4. Break-Before-Make Switching
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
5. Low Leakage
Leakage currents in the range of 20 pA make these multiplexers
suitable for high precision circuits.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.

1 page




ADG528A pdf
PIN CONFIGURATIONS
DIP/SOIC
PLCC
ADG528A/ADG529A
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs2
Voltage at S, D . . . . . . . . . VSS – 2 V to VDD + 2 V or 20 mA,
whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current, S or D
1 ms duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs1
Voltage at A, EN, WR, RS . . . . . . VSS – 4 V to VDD + 4 V or
20 mA, whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should
be limited to the maximum rating above.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option1
ADG528AKN
ADG528AKP
ADG528AKP-REEL
ADG528ABQ
ADG528ATQ
ADG528ABCHIPS
ADG528ATCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
PDIP
PLCC
PLCC
CERDIP
CERDIP
DIE
DIE
N-18
P-20A
P-20A
Q-18
Q-18
ADG529AKN
ADG529AKP
ADG529AKRW
ADG529AKRW-REEL
ADG529AKRW-REEL7
ADG529ABQ
ADG529ATQ
ADG529ABCHIPS
ADG529ATCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
PDIP
PLCC
SOIC
SOIC
SOIC
CERDIP
CERDIP
DIE
DIE
N-18
P-20A
RW-18
RW-18
RW-18
Q-18
Q-18
NOTES
1N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; RW = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE

5 Page





ADG528A arduino
ADG528A/ADG529A
OUTLINE DIMENSIONS
18-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-18)
Dimensions shown in inches and (millimeters)
0.005
(0.13)
MIN
PIN 1
18
1
0.098 (2.49)
MAX
10
9
0.200
(5.08)
MAX
0.960 (24.38) MAX
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
SEATING
PLANE
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
15 0.008 (0.20)
0
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
18-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-18)
Dimensions shown in millimeters and (inches)
11.75 (0.4626)
11.35 (0.4469)
18 10
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 9 10.00 (0.3937)
0.30 (0.0118)
0.10 (0.0039)
1.27
COPLANARITY (0.0500)
0.10 BSC
2.65 (0.1043)
2.35 (0.0925)
0.75
0.25
(0.0295)
(0.0098)
؋
45؇
8؇
0.51 (0.0201) SEATING
0.31 (0.0122) PLANE
0.33 (0.0130) 0؇
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
–11–

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