ADG1422 Datasheet PDF - Analog Devices
| Part Number | ADG1422 | |
| Description | iCMOS Dual SPST Switches | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Data Sheet
2.1 Ω On Resistance, ±15 V/+12 V/±5 V
iCMOS Dual SPST Switches
ADG1421/ADG1422/ADG1423
FEATURES
2.1 Ω on resistance
0.5 Ω maximum on resistance flatness
Up to 250 mA continuous current
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages
APPLICATIONS
Automatic test equipment
Data acquisition systems
Relay replacements
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1421/ADG1422/ADG1423 contain two independent
single-pole/single-throw (SPST) switches. The ADG1421 and
ADG1422 differ only in that the digital control logic is inverted.
The ADG1421 switches are turned on with Logic 1 on the
appropriate control input, and Logic 0 is required for the
ADG1422. The ADG1423 has one switch with digital control
logic similar to that of the ADG1421; the logic is inverted on
the other switch. The ADG1423 exhibits break-before-make
switching action for use in multiplexer applications. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
The iCMOS® (industrial CMOS) modular manufacturing process
combines high voltage, complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development
of a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no other generation of high voltage
parts has achieved. Unlike analog ICs using conventional CMOS
processes, iCMOS components can tolerate high supply voltages
while providing increased performance, dramatically lower
power consumption, and reduced package size.
FUNCTIONAL BLOCK DIAGRAM
ADG1421
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1. ADG1421 Functional Block Diagram
ADG1422
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 2. ADG1422 Functional Block Diagram
ADG1423
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 3. ADG1423 Functional Block Diagram
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. The iCMOS construction ensures
ultralow power dissipation, making the part ideally suited for
portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2.4 Ω maximum on resistance at 25°C.
2. Minimum distortion.
3. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
4. No VL logic power supply required.
5. 10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
ADG1421/ADG1422/ADG1423
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD (ADG1423 Only)
Charge Injection
−40°C to −40°C to
25°C +85°C
+125°C
4.5
5.2 6.2
0.04
0.18 0.2
1.3
1.6 1.85
VDD to VSS
7
0.21
2
±0.05
±0.5
±0.05
±0.5
±0.1
±1
±2
±2
±2
±75
±75
±75
0.005
4
2.0
0.8
±0.1
285
370 460
220
295 350
85
82
520
395
45
Off Isolation
−60
Channel-to-Channel Crosstalk
−70
Total Harmonic Distortion + Noise
0.04
−3 dB Bandwidth
Insertion Loss
150
0.25
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
1 Guaranteed by design, not subject to production test.
25
30
100
0.001
0.001
1.0
1.0
±4.5/±16.5
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VS = ±4.5 V, IS = −10 mA; see Figure 23
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5V; IS = −10 mA
VS = ±4.5 V, IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
VS = VD = ±4.5 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; see Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 32
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
VS = 0V, f = 1 MHz
VS = 0V, f = 1 MHz
VS = 0V, f = 1 MHz
VDD = 5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
Ground = 0 V
Rev. A | Page 5 of 16
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| Information | Total 16 Pages | |
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