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PDF ADG1439 Data sheet ( Hoja de datos )
| Número de pieza | ADG1439 | |
| Descripción | iCMOS Multiplexers/Matrix Switches | |
| Fabricantes | Analog Devices | |
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Data Sheet
Serially Controlled, ±15 V/+12 V/±5 V, 8-Channel/
4-Channel, iCMOS Multiplexers/Matrix Switches
ADG1438/ADG1439
FEATURES
Serial interface up to 50 MHz
SDO daisy-chaining option
9.5 Ω on resistance at 25°C
1.6 Ω on-resistance flatness
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Rail-to-rail operation
20-lead TSSOP and 20-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
GENERAL DESCRIPTION
The ADG1438 and ADG1439 are CMOS analog matrix switches
with a serially controlled 3-wire interface. The ADG1438 is an
8-channel matrix switch, and the ADG1439 is a dual 4-channel
matrix switch.
The ADG1438/ADG1439 use a versatile 3-wire serial interface
that operates at clock rates of up to 50 MHz and is compatible
with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The output of the shift register, SDO, enables a number
of the ADG1438/ADG1439 devices to be daisy-chained. On
power-up, the internal shift register contains all zeros, and all
switches are in the off state.
Each switch conducts equally well in both directions when on,
making these devices suitable for both multiplexing and
demultiplexing applications. Because each switch is turned on
or off by a separate bit, these devices can also be configured as a
type of switch array, where any, all, or none of the eight switches
can be closed at any time. The input signal range extends to the
supply rails. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and
gain switching applications where low distortion is critical.
iCMOS® construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAMS
ADG1438
S1
D
S8
INPUT SHIFT
REGISTER
SDO
SCLK SYNC DIN RESET
Figure 1.
ADG1439
S1A
S4A
DA
S1B
DB
S4B
INPUT SHIFT
REGISTER
SDO
SCLK SYNC DIN RESET
Figure 2.
PRODUCT HIGHLIGHTS
1. 50 MHz serial interface.
2. 9.5 Ω on resistance.
3. 1.6 Ω on-resistance flatness.
4. 3 V logic-compatible digital input, VINH = 2.0 V, VINL = 0.8 V.
Table 1. Related Devices
Device No.
ADG1408/ADG1409
Description
Low on resistance, parallel
interface, 4-/8-channel ±15 V
multiplexers
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
−40°C to
+25°C +85°C
18
−40°C to
+125°C
0 to VDD
Unit
V
Ω typ
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
ADG1438
ADG1439
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
21.5 26
0.55
1.2 1.6
5
6 6.9
±0.02
±0.15
±0.02
±0.25
±0.25
±0.05
±0.3
±1
±3
±1.5
±3
±0.001
Digital Input Capacitance, CIN
LOGIC OUTPUTS (SDO)
Output Low Voltage, VOL1
4
High Impedance Leakage Current 0.001
High Impedance Output
Capacitance1
DYNAMIC CHARACTERISTICS1
Break-Before-Make Time Delay, tBBM
4
115
Transition Time, tTRANSITION
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG1438
ADG1439
155
195 235
7
−70
−70
58
105
28.5
1.8
7.3
±2
±12
±6
±12
2.0
0.8
±0.1
0.4
0.6
±1
60
260
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
V max
V max
µA typ
µA max
pF typ
ns typ
ns min
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
MHz typ
ADG1438/ADG1439
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA; see Figure 27.
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS =
−10 mA.
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS =
−10 mA.
VDD = 10.8 V.
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28.
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28.
VS = VD = 1 V or 10 V; see Figure 29.
VIN = VGND or VL.
ISINK = 3 mA.
ISINK = 6 mA.
RL = 100 Ω, CL = 35 pF.
VS1 = VS2 = 8 V; see Figure 31.
RL = 100 Ω, CL = 35 pF.
VS = 8 V; see Figure 30.
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32.
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33.
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34.
RL = 50 Ω, CL = 5 pF; see Figure 35.
Rev. B | Page 5 of 20
5 Page 
Data Sheet
ADG1438/ADG1439
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SCLK 1
20 SYNC
VDD 2
DIN 3
GND 4
NIC 5
S1 6
19 VL
18 SDO
ADG1438
TOP VIEW 17 RESET
(Not to Scale) 16 VSS
15 S5
S2 7
14 S6
S3 8
13 S7
S4 9
12 S8
D 10
11 NIC
NIC = NO INTERNAL CONNECTION
Figure 5. ADG1438 Pin Configuration (TSSOP)
DIN 1
GND 2
S1 3
S2 4
S3 5
ADG1438
TOP VIEW
(Not to Scale)
15 RESET
14 VSS
13 S5
12 S6
11 S7
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.
Figure 6. ADG1438 Pin Configuration (LFCSP)
Table 10. ADG1438 Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1 19
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
2 20
VDD Most Positive Power Supply Potential.
31
DIN Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
42
GND Ground (0 V) Reference.
5, 11 7, 9 NIC No Internal Connection.
63
S1 Source Terminal 1. Can be an input or an output.
74
S2 Source Terminal 2. Can be an input or an output.
85
S3 Source Terminal 3. Can be an input or an output.
96
S4 Source Terminal 4. Can be an input or an output.
10 8 D Drain Terminal. Can be an input or an output.
12 10 S8 Source Terminal 8. Can be an input or an output.
13 11 S7 Source Terminal 7. Can be an input or an output.
14 12 S6 Source Terminal 6. Can be an input or an output.
15 13 S5 Source Terminal 5. Can be an input or an output.
16 14 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected
to ground.
17 15
RESET
Active Low Logic Input. When this pin is low, all switches are open, and the appropriate registers
are cleared to 0.
18 16
SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for
reading back the data in the shift register for diagnostic purposes. The serial data is transferred on
the rising edge of SCLK and is valid on the falling edge of the clock. This is an open-drain output
that should be pulled to the VL supply with an external 1 kΩ resistor.
19 17
VL
Logic Power Supply Input. Operates from 2.7 V to 5.5 V.
20 18
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch
condition.
N/A1
0
EPAD
The exposed pad is tied to the substrate, VSS.
1 N/A means not applicable
Rev. B | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADG1439.PDF ] | |
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