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PDF ADA2200 Data sheet ( Hoja de datos )
| Número de pieza | ADA2200 | |
| Descripción | Synchronous Demodulator and Configurable Analog Filter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Demodulates signal input bandwidths to 30 kHz
Programmable filter enables variable bandwidths
Filter tracks input carrier frequency
Programmable reference clock frequency
Flexible system interface
Single-ended/differential signal inputs and outputs
Rail-to-rail outputs directly drive analog-to-digital
converters (ADCs)
Phase detection sensitivity of 9.3m°θREL rms
Configurable with 3-wire and 4-wire serial port interface (SPI) or
seamless boot from I2C EEPROMs
Very low power operation
395 μA at fCLKIN = 500 kHz
Single supply: 2.7 V to 3.6 V
Specified temperature range: −40°C to +85°C
16-lead TSSOP package
APPLICATIONS
Synchronous demodulation
Sensor signal conditioning
Lock-in amplifiers
Phase detectors
Precision tunable filters
Signal recovery
Control systems
GENERAL DESCRIPTION
The ADA2200 is a sampled analog technology1 synchronous
demodulator for signal conditioning in industrial, medical, and
communications applications. The ADA2200 is an analog input,
sampled analog output device. The signal processing is performed
entirely in the analog domain by charge sharing among capacitors,
which eliminates the effects of quantization noise and rounding
errors. The ADA2200 includes an analog domain, low-pass
decimation filter, a programmable infinite impulse response
(IIR) filter, and a mixer. This combination of features reduces
ADC sample rates and lowers the downstream digital signal
processing requirements.
The ADA2200 acts as a precision filter when the demodulation
function is disabled. The filter has a programmable bandwidth
and tunable center frequency. The filter characteristics are highly
stable over temperature, supply, and process variation.
Single-ended and differential signal interfaces are possible on both
input and output terminals, simplifying the connection to other
1 Patent pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Synchronous Demodulator
and Configurable Analog Filter
ADA2200
FUNCTIONAL BLOCK DIAGRAM
VDD
INP
INN
CLKIN
ADA2200
fSI
÷2m
8
LPF
fSO
÷8
PROGRAM
FILTER
fM
÷2n+1
90° VCM
XOUT
CLOCK
GEN
CONTROL
REGISTERS
SPI/I2C
MASTER
OUTP
OUTN
VOCM
RCLK/SDO
SCLK/SCL
SDIO/SDA
CS/A0
SYNCO
GND
RST BOOT
Figure 1.
components of the signal chain. The low power consumption and
rail-to-rail operation is ideal for battery-powered and low
voltage systems.
The ADA2200 can be programmed over its SPI-compatible
serial port or can automatically boot from the EEPROM
through its I2C interface. On-chip clock generation produces a
mixing signal with a programmable frequency and phase. In
addition, the ADA2200 synchronization output signal eases
interfacing to other sampled systems, such as data converters
and multiplexers.
The ADA2200 is available in a 16-lead TSSOP package. Its
performance is specified over the industrial temperature range
of −40°C to +85°C. Note that throughout this data sheet,
multifunction pins, such as SCLK/SCL, are referred to either by
the entire pin name or by a single function of the pin, for
example, SCLK, when only that function is relevant.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADA2200
Data Sheet
Parameter
DIGITAL I/O
Logic Thresholds
Input Voltage
Low
High
Output Voltage
Low
High
Maximum Output Current
Input Leakage
Internal Pull-Up Resistance
CRYSTAL OSCILLATOR
Internal Feedback Resistor
CLKIN Capacitance
XOUT Capacitance
POWER REQUIREMENTS
Power Supply Voltage Range
Total Supply Current Consumption
Test Conditions/Comments
All inputs/outputs
While sinking 200 µA
While sourcing 200 µA
Sink or source
BOOT and RST only
Min Typ
Max Unit
0.8 V
2.0 V
VDD − 0.4
40
0.4 V
V
8 mA
1 µA
kΩ
500 kΩ
2 pF
2 pF
2.7 3.6 V
395 485 µA
1 See the Terminology section.
2 Common-mode signal swept from fMOD − 1 kHz to fMOD + 1 kHz. Output measured at frequency offset from fMOD. For example, a common-mode signal at fMOD − 500 Hz is
measured at 500 Hz.
3 The input impedance is equal to a 4 pF capacitor switched at fCLKIN. Therefore, the input impedance = 1012/(2πfCLKIN × 4).
SPI TIMING CHARACTERISTICS
VDD = 2.7 V to 3.6 V, default register configuration, TA = −40 to +85°C, unless otherwise noted.
Table 2. SPI Timing
Parameter
Test Conditions/Comments
fSCLK 50% ± 5% duty cycle
tCS CS to SCLK edge
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
tDOCS Data output valid after CS edge
tSFS CS high after SCLK edge
Min
2
10
10
2
2
2
Typ
Max Unit
20 MHz
ns
ns
ns
20 ns
ns
ns
1 ns
1 ns
10 ns
10 ns
1 ns
ns
Rev. 0 | Page 4 of 24
5 Page 
ADA2200
TERMINOLOGY
Cycle Mean
The cycle mean is the average of all the output samples
(OUTP/OUTN) over one RCLK period. In the default
configuration, there are eight output samples per RCLK cycle;
thus, the cycle mean is the average of eight consecutive output
samples. If the device is reconfigured such that the frequency of
RCLK is fSO/4, then the cycle mean is the average of four
consecutive output samples.
Conversion Gain
Conversion gain is calculated as follows:
I 2 +Q2
Conversion Gain =
V IN
where:
I is the offset corrected cycle mean, PHASE90 bit = 0.
Q is the offset corrected cycle mean, PHASE90 bit = 1.
VIN is the rms value of the input voltage.
The offset corrected cycle mean = cycle mean − output offset.
Relative Phase (θREL)
Relative phase is the phase difference between the rising
positive zero crossing of a sine wave at the INN/INP inputs
relative to the next rising edge of RCLK.
RCLK
Data Sheet
Phase Delay (°θDELAY)
The phase delay is the relative phase (θREL) that produces a zero
cycle mean output value for a sine wave input with a frequency
equal to fRCLK. The phase delay is the relative phase value that
corresponds to the positive zero crossing of the phase measurement
transfer function.
Phase Measurement Transfer Function
Figure 15 shows the cycle mean value of the output for a
1 V rms input sine wave as θREL is swept from 0° to 360°.
1.2
1.0
0.8
0.6
0.4
83°
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
45 90 135 180 225 270 315 360
RELATIVE PHASE (θREL)
Figure 15. Phase Transfer Function with Phase Delay of 83°, 1 V rms Input
0 50 100 150 200 250 300 350
PHASE (Degrees)
RELATIVE
PHASE = 37°
INP/INN
Figure 14. Example Showing Relative Phase, θREL, of 37°
Rev. 0 | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADA2200.PDF ] | |
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