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PDF ADAU7002 Data sheet ( Hoja de datos )
| Número de pieza | ADAU7002 | |
| Descripción | Stereo PDM-to-I2S or TDM Conversion IC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Stereo PDM-to-I2S or
TDM Conversion IC
ADAU7002
FEATURES
64× decimation of a stereo pulse density modulation (PDM)
bit stream to pulse code modulation (PCM) audio data
Slave I2S or time division multiplexed (TDM) output interface
Configurable TDM slots
I/O supply operation: 1.62 V to 3.6 V
64× output sample rate PDM clock
64×/128×/192×/256×/384×/512× output sample rate BCLK
Automatic BCLK ratio detection
Output sample rate: 4 kHz to 96 kHz
Automatic PDM CLK drive at 64× the sample rate
Automatic power down with BCLK removal
0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply
Shutdown current: <1 μA
8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP
Power-on reset
GENERAL DESCRIPTION
The ADAU7002 converts a stereo PDM bit stream into a PCM
output. The source for the PDM data can be two microphones
or other PDM sources. The PCM audio data is output on a
serial audio interface port in either I2S or TDM format.
The ADAU7002 is specified over the commercial temperature
range (−40°C to +85°C). It is available in a halide-free, 8-ball,
1.56 mm × 0.76 mm, wafer level chip scale package (WLCSP).
APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics
FUNCTIONAL BLOCK DIAGRAM
1.62V TO 3.6V
PDM_CLK
PDM_DAT
CONFIG GND
IOVDD
PDM
INPUT
PORT
DIGITAL
DECIMATION
FILTERING
I2S
OUTPUT
PORT
Figure 1.
ADAU7002
BCLK
LRCLK
SDATA
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADAU7002
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter
IOVDD Supply Voltage
Input Voltage
ESD Susceptibility
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
3.6 V
3.6 V
4 kV
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA is determined according to JESD51-9 on a 4-layer
printed circuit board (PCB) with natural convection cooling.
Table 3. Thermal Resistance
Package Type
8-ball, 1.56 mm × 0.76 mm WLCSP
θJA Unit
90 °C/W
ESD CAUTION
Rev. B | Page 4 of 16
5 Page 
ADAU7002
Serial Port Timing
tBIH
BCLK
LRCLK
tBIL
tLIS
SDATA
TDM MODE
tSODM
MSB
MSB – 1
SDATA
I2S JUSTIFIED
MODE
tSODM
MSB
Figure 13. Serial Port Timing Diagram
IOVDD = 1.62 V to 3.63 V, load capacitance = 25 pF, unless otherwise noted.
Table 7. I2S/TDM Timing Parameters
Parameter
BCLK Pulse Width High
BCLK Pulse Width Low
LRCLK Setup Time
LRCLK Hold Time
Time from BCLK Falling
Symbol
tBIH
tBIL
tLIS
tLIH
tSODM
tMIN
10
10
10
10
Data Sheet
tLIH
tMAX Unit
ns
ns
ns
ns
18 ns
LRCLK
BCLK
SDATA
I2S LEFT CHANNEL
20
BCLKs
TRISTATE
I2S RIGHT CHANNEL
Figure 14. I2S, CONFIG Pin Tied to IOVDD
TRISTATE
LRCLK
BCLK
SDATA
LEFT
20
BCLKs
SLOT 1
RIGHT
TRISTATE
TRISTATE
TRISTATE
TRISTATE
TRISTATE
TRISTATE
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
Figure 15. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND
SLOT 7
Rev. B | Page 10 of 16
SLOT 8
11 Page | ||
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