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PDF ADV7630 Data sheet ( Hoja de datos )
| Número de pieza | ADV7630 | |
| Descripción | 2.25 GHz XpressView HDMI 1:2 Splitter | |
| Fabricantes | Analog Devices | |
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Data Sheet
2.25 GHz XpressView
HDMI 1:2 Splitter with 4:1 Input Mux
ADV7630
FEATURES
2.25 GHz TMDS HDMI 1:2 splitter with 4:1 input mux
High-Definition Multimedia Interface (HDMI) supported
All mandatory and additional 3D video formats supported
CEC 1.4-compatible
225 MHz maximum TMDS clock frequency
XpressView fast switching on all HDMI input ports
36-/30-bit per pixel Deep Color and 24-bit per pixel color
support
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal HDCP keys
HDCP repeater support
Up to 127 KSVs supported
Integrated CEC controller
5 V detect and hot plug assert for each HDMI port
EDID data extraction on HDMI outputs
Hot plug detection (HPD) input on HDMI outputs
General
Interrupt controller with interrupt output
On-chip 5 V regulator for 5 V HDMI cable power support
Software libraries, driver, and application available
Internal EDID RAM
128-lead 14 mm × 14 mm TQFP_EP package
APPLICATIONS
Video conferencing
HDTV
AVR, HTiB
Soundbar
Video switch
HDMI splitter
HDMI 1
TMDS
DDC
FUNCTIONAL BLOCK DIAGRAM
ADV7630
HDMI 2
TMDS
DDC
HDMI 3
TMDS
DDC
DEEP
COLOR
HDMIRX
4:1
MUX
1:2
SPLITTER
TMDS
DDC
HDMI TXA
TMDS
DDC
HDMI TXB
HDMI 4
TMDS
DDC
HDCP
KEYS
FAST
SWITCH
I2C
INT
CEC
TX EDID/HDCP
BUFFER
CEC
I2C INT
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADV7630
Data Sheet
SPECIFICATIONS
DVDD, TXA_PVDD, TXB_PVDD, CVDD, TX_AVDD at 1.71 V to 1.89 V; DVDDIO, TVDD, SYS_3P3V at 3.14 V to 3.46 V; TMIN to
TMAX = 0oC to 70oC, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
VIH Digital inputs
VIL Digital inputs
IIN RESET, CS, EP_MISO
Other digital inputs
2V
0.8 V
40 µA
10 µA
Input Capacitance1
DIGITAL INPUTS (5 V TOLERANT)2
CIN
Excluding differential HDMI inputs
20 pF
Input High Voltage
Input Low Voltage
High Impedance Leakage Current
VIH
VIL
ILEAK
2.6
DDCA_SCL, DDCB_SCL, DDCC_SCL, DDCD_SCL,
DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA,
TXA_DDC_SDA, TXB_DDC_SDA3
30
V
0.8 V
µA
TXA_HPD, TXB_HPD
10 µA
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
VOH
VOL
ILEAK
2.4
DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA,
TXA_DDC_SDA, TXB_DDC_SDA, TXA_DDC_SCL,
TXB_DDC_SCL3
30
V
0.4 V
µA
Output Capacitance1
POWER REQUIREMENTS1
All other digital pins
COUT Excluding non-tristable outputs4
10 µA
20 pF
Digital Core Power Supply
DVDD
1.71 1.8
1.89 V
Digital I/O Power Supply
DVDDIO
3.14 3.3
3.46 V
PLL Power Supply TXA
TXA_PVDD
1.71 1.8
1.89 V
PLL Power Supply TXB
TXB_PVDD
1.71 1.8
1.89 V
Terminator Power Supply
TVDD
3.14 3.3
3.46 V
Comparator Power Supply
CVDD
1.71 1.8
1.89 V
System Power Supply
SYS_3P3V
3.14 3.3
3.46 V
TX Analog Power Supply
TX_AVDD
1.71 1.8
1.89 V
Power-Up Time
Test Condition 1
tPWRUP
25 ms
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Terminator Power Supply
Comparator Power Supply
System Power Supply
TX Analog Power Supply
IDVDD
IDVDDIO
I5
TX_PVDD
ITVDD
ICVDD
ISYS_3P3V
ITX_AVDD
Test Condition 1
Test Condition 1
Test Condition 1
Test Condition 1
Test Condition 1
Test Condition 1
Test Condition 1
277 303 mA
0.13 0.13 mA
85.9 97.6 mA
226 227 mA
307 328 mA
2.21 3.23 mA
33.0 34.9 mA
Rev. 0 | Page 4 of 16
5 Page 
ADV7630
Data Sheet
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type
0
GND
Ground
1
RESET
Miscellaneous
digital
2 to 7, 55,
93 to 96
DNC
Do not connect
8 INT1 Miscellaneous
digital
9
CLK_IN
Digital input
10 CEC Digital
input/output
11
DVDDIO
Power
12 SDA Digital
input/output
13 SCL
Digital input
14 CS
Digital input
15
DVDD
Power
16
TXB_PVDD
Power
17
TXB_PVDD
Power
18, 40
19
NC
TXB_PVDD
Not connected
Power
20
TXB_HPD
Digital input
21
TX_AVDD
Power
22
TXB_C−
HDMI output
23
TXB_C+
HDMI output
24
TX_AVDD
Power
25
TXB_0−
HDMI output
26
TXB_0+
HDMI output
27
TX_AVDD
Power
28
TXB_1−
HDMI output
29
TXB_1+
HDMI output
30
TXB_2−
HDMI output
31
TXB_2+
HDMI output
32
TX_AVDD
Power
33 TXB_DDC_SDA Digital
input/output
34 TXB_DDC_SCL Digital output
Description
The Exposed Pad Should be Connected to GND.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7630 circuitry.
Do not connect to this pin.
Interrupt Output Pin.
Input Pin for a 3.3 V 27.000 MHz Clock Oscillator. The following frequencies are also
supported: 24 MHz, 24.576 MHz, and 28.63636 MHz.
Consumer Electronic Control Channel.
Digital I/O Supply Voltage (3.3 V).
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
I2C Port Serial Clock Input. SCL is the clock line for the control port.
Chip Select Pin. Pulling this pin up causes the I2C state machine to ignore I2C
transmission. This pin has internal pull-down.
Digital Core Supply Voltage (1.8 V).
1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It
should be kept separately from TXA_PVDD to avoid possible crosstalk. This power
supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with
10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the
package.
1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It
should be kept separately from TXA_PVDD to avoid possible crosstalk. This power
supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with
10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the
package.
This pin is not connected internally (see Figure 5).
1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It
should be kept separately from TXA_PVDD to avoid possible crosstalk. This power
supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with
10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the
package.
Hot Plug Detect Signal of HDMI Output Port B. This pin indicates to the interface whether
the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels.
1.8 V Power Supply for TMDS Outputs.
TMDS Clock Output Complement of HDMI Output Port B.
TMDS Clock Output True of HDMI Output Port B.
1.8 V Power Supply for TMDS Outputs.
TMDS Output Channel 0 Complement of HDMI Output Port B.
TMDS Output Channel 0 True of HDMI Output Port B.
1.8 V Power Supply for TMDS Outputs.
TMDS Output Channel 1 Complement of HDMI Output Port B.
TMDS Output Channel 1 True of HDMI Output Port B.
TMDS Output Channel 2 Complement of HDMI Output Port B.
TMDS Output Channel 2 True of HDMI Output Port B.
1.8 V Power Supply for TMDS Outputs.
HDCP Master Serial Data of HDMI Output Port B. TXB_DDC_SDA is a 3.3 V open-drain
input/output that is 5 V tolerant.
HDCP Master Serial Clock of HDMI Output Port B. TXB_DDC_SCL is a 3.3 V open-drain
output that is 5 V tolerant.
Rev. 0 | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADV7630.PDF ] | |
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