PDF ADP5586 Data sheet ( Hoja de datos )

Número de pieza	ADP5586
Descripción	Keypad Decoder and I/O Port Expander
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Keypad Decoder and I/O Port Expander ADP5586 FEATURES 16-element FIFO for event recording 10 configurable I/Os allowing for such functions as Keypad decoding for a matrix of up to 5 × 5 Key press/release interrupts GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open drain Programmable logic block Pulse generators Periods and on times Above 30 sec in 125 ms increments Up to 255 ms in 1 ms increments Reset generator I2C interface with Fast-mode Plus (Fm+) support of up to 1 MHz Open-drain interrupt output 16-ball WLCSP, 1.59 mm × 1.59 mm APPLICATIONS Keypad entries and input/output expansion capabilities Smartphones, remote controls, and cameras Healthcare, industrial, and instrumentation GENERAL DESCRIPTION The ADP5586 is a 10-input/output port expander with a built-in keypad matrix decoder, programmable logic, reset generator, and pulse generators. Input/output expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs. The ADP5586 handles all key scanning and decoding and can flag the main processor, via an interrupt line, that new key events have occurred. GPI changes and logic changes can also be tracked RST/R5 SDA SCL FUNCTIONAL BLOCK DIAGRAM VDD GND ADP5586 UVLO POR OSCILLATOR I2C INTERFACE R0 R1 R2 R3 R4 I/O CONFIG C0 C1 C2 C3 C4 KEY SCAN AND DECODE GPI SCAN AND DECODE LOGIC PULSE GEN 1 PULSE GEN 2 RESET GEN Figure 1. REGISTERS INT as events via the FIFO, eliminating the need to monitor different registers for event changes. The ADP5586 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C-compatible interface. The ADP5586 eliminates the need for the main processor to monitor the keypad, thus reducing power consumption and/or increasing processor bandwidth for performing other functions. The programmable logic functions allow common logic require- ments to be integrated as part of the GPIO expander, thus saving board area and cost. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADP5586 Data Sheet I2C TIMING SPECIFICATIONS Table 2. Parameter I2C TIMING SPECIFICATIONS Delay from UVLO/RST Inactive to I2C Access fSCL tHIGH tLOW tSU; DAT tHD; DAT tSU; STA tHD; STA tBUF tSU; STO tVD; DAT tVD; ACK tR tF tSP CB1 Description SCL clock frequency SCL high time SCL low time Data setup time Data hold time Setup time for repeated start Hold time for start/repeated start Bus free time for stop and start conditions Setup time for stop condition Data valid time Data valid acknowledge Rise time for SCL and SDA Fall time for SCL and SDA Pulse width of suppressed spike Capacitive load for each bus line 1 CB is the total capacitance of one bus line in picofarads (pF). Timing Diagram tF tR tSU; DAT 70% SDA 30% 70% 30% tF tHD; DAT SCL S 70% 30% 70% 30% tHD; STA 1/fSCL FIRST CLOCK CYCLE SDA tSU; STA tHD; STA tSP tR 70% 30% tLOW tHIGH tVD; DAT 70% 30% tBUF tVD; ACK tSU; STO SCL VIL = 0.3V × VDD VIH = 0.7V × VDD Sr 70% 30% NINTH CLOCK P Figure 2. I2C Interface Timing Diagram S Min Max 60 0 1000 0.26 0.5 50 0 0.26 0.26 0.5 0.26 0.45 0.45 120 120 0 50 550 NINTH CLOCK Unit μs kHz μs μs ns μs μs μs μs μs μs μs ns ns ns pF Rev. 0 \| Page 4 of 44 5 Page ADP5586 KEY SCAN CONTROL General The 10 input/output pins can be configured to decode a keypad matrix up to a maximum size of 25 switches (5 × 5 matrix) using the PIN_CONFIG_A, PIN_CONFIG_B, and PIN_CONFIG_C registers (Registers 0x3A through 0x3C). Smaller matrices can also be configured, making the unused row and column pins available for other I/O functions. The R0 through R4 I/O pins comprise the rows of the keypad matrix. The C0 through C4 I/O pins comprise the columns of the keypad matrix. Pins that are used as rows are pulled up via the internal 300 kΩ (or 100 kΩ) resistors. Pins that are used as columns are driven low via the internal NMOS current sink. VDD KEY SCAN CONTROL C0 C1 C2 R0 R1 R2 123 45 6 78 9 3 × 3 KEYPAD MATRIX Figure 8. Simplified Key Scan Block Data Sheet Figure 8 shows a simplified representation of the key scan block using three row pins and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low. The key scanner operates by checking the row pins to see if they are low. If Switch 6 in the matrix is pressed, R1 connects to C2. The key scan circuit senses that one of the row pins has been pulled low, and a key scan cycle begins. Key scanning involves driving all column pins high, then driving each column pin low, one at a time, and sensing whether a row pin is low. All row/column pairs are scanned; therefore, if multiple keys are pressed, they are detected. To prevent a glitch or narrow press time from being registered as a valid key press, the key scanner requires that the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan and wait for as long as the key is pressed. If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled high. The key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner. Up to two full wait/scan cycles may be required for a key to register as released. When the key registers as released, and no other keys are pressed, the key scanner returns to idle mode. For the remainder of this data sheet, the press/release status of a key is represented as simply a logic signal in the figures. A logic high level represents the key status as pressed, and a logic low level represents released. This eliminates the need to draw individual row/column signals when describing key events. KEY PRESSED KEY x KEY RELEASED KEY RELEASED Figure 9. Logic Low: Key Released; Logic High: Key Pressed Rev. 0 \| Page 10 of 44 11 Page

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