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Analog Devices - High Speed M-LVDS Transceivers

Numéro de référence ADN4697E
Description High Speed M-LVDS Transceivers
Fabricant Analog Devices 
Logo Analog Devices 





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Data Sheet
3.3 V, 200 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
ADN4691E/ADN4693E/ADN4696E/ADN4697E
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV
Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4691E/ADN4696E) and 14-lead
(ADN4693E/ADN4697E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
GENERAL DESCRIPTION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV
is implemented on the bus pins. The devices adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-
644 LVDS devices with additional multipoint capabilities.
The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of
hysteresis so that slow-changing signals or loss of input does not
lead to output oscillations. The ADN4696E/ADN4697E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADN4691E/
ADN4696E
RO R
RE A
B
DE
DI D
GND
Figure 1.
VCC
ADN4693E/
ADN4697E
RO R
A
B
RE
DE
DI D
Z
Y
GND
Figure 2.
The devices are available as half-duplex in an 8-lead SOIC package
(the ADN4691E/ADN4696E) or as full-duplex in a 14-lead
SOIC package (the ADN4693E/ADN4697E). A selection table
for the ADN4690E to ADN4697E devices is shown in Table 1.
Table 1. ADN4690E to ADN4697E Selection Table
Part No. Receiver Data Rate SOIC
Duplex
ADN4690E Type 1
100 Mbps 8-lead Half
ADN4691E Type 1
200 Mbps 8-lead Half
ADN4692E Type 1
100 Mbps 14-lead Full
ADN4693E Type 1
200 Mbps 14-lead Full
ADN4694E Type 2
100 Mbps 8-lead Half
ADN4695E Type 2
100 Mbps 14-lead Full
ADN4696E Type 2
200 Mbps 8-lead Half
ADN4697E Type 2
200 Mbps 14-lead Full
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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