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PDF ADN4691E Data sheet ( Hoja de datos )
| Número de pieza | ADN4691E | |
| Descripción | High Speed M-LVDS Transceivers | |
| Fabricantes | Analog Devices | |
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Data Sheet
3.3 V, 200 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
ADN4691E/ADN4693E/ADN4696E/ADN4697E
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV
Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4691E/ADN4696E) and 14-lead
(ADN4693E/ADN4697E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
GENERAL DESCRIPTION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV
is implemented on the bus pins. The devices adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-
644 LVDS devices with additional multipoint capabilities.
The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of
hysteresis so that slow-changing signals or loss of input does not
lead to output oscillations. The ADN4696E/ADN4697E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADN4691E/
ADN4696E
RO R
RE A
B
DE
DI D
GND
Figure 1.
VCC
ADN4693E/
ADN4697E
RO R
A
B
RE
DE
DI D
Z
Y
GND
Figure 2.
The devices are available as half-duplex in an 8-lead SOIC package
(the ADN4691E/ADN4696E) or as full-duplex in a 14-lead
SOIC package (the ADN4693E/ADN4697E). A selection table
for the ADN4690E to ADN4697E devices is shown in Table 1.
Table 1. ADN4690E to ADN4697E Selection Table
Part No. Receiver Data Rate SOIC
Duplex
ADN4690E Type 1
100 Mbps 8-lead Half
ADN4691E Type 1
200 Mbps 8-lead Half
ADN4692E Type 1
100 Mbps 14-lead Full
ADN4693E Type 1
200 Mbps 14-lead Full
ADN4694E Type 2
100 Mbps 8-lead Half
ADN4695E Type 2
100 Mbps 14-lead Full
ADN4696E Type 2
200 Mbps 8-lead Half
ADN4697E Type 2
200 Mbps 14-lead Full
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages
VA (V)
VB (V)
+2.4 0
0 +2.4
+3.8 +3.65
+3.8 +3.75
−1.25
−1.4
−1.35
−1.4
Input Voltage, Differential
VID (V)
+2.4
−2.4
+0.15
+0.05
+0.15
+0.05
Input Voltage, Common Mode
VIC (V)
+1.2
+1.2
+3.725
+3.775
−1.325
−1.375
Receiver Output
RO (V)
H
L
H
L
H
L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol Min Typ Max
DRIVER
Maximum Data Rate
200
Propagation Delay
tPLH, tPHL
1
1.5 2.4
Differential Output Rise/Fall Time
tR, tF
1
1.6
Pulse Skew |tPHL – tPLH|
tSK 0 100
Part-to-Part Skew2
tSK(PP)
1
Period Jitter, RMS (1 Standard Deviation)3 tJ(PER)
23
Peak-to-Peak Jitter3, 5
tJ(PP) 30 130
Disable Time from High Level
tPHZ
7
Disable Time from Low Level
tPLZ
7
Enable Time to High Level
tPZH
7
Enable Time to Low Level
tPZL
7
RECEIVER
Propagation Delay
tRPLH, tRPHL 2 4 6
Rise/Fall Time
tR, tF
1
2.3
Pulse Skew |tRPHL – tRPLH|
tSK
Type 1 Receiver (ADN4691E, ADN4693E)
100 300
Type 2 Receiver (ADN4696E, ADN4697E)
300 500
Part-to-Part Skew2
tSK(PP)
1
Period Jitter, RMS (1 Standard Deviation)3 tJ(PER)
47
Peak-to-Peak Jitter3, 5
tJ(PP)
Type 1 Receiver (ADN4691E, ADN4693E) tJ(PP)
300 700
Type 2 Receiver (ADN4696E, ADN4697E)
450 800
Disable Time from High Level
tRPHZ
10
Disable Time from Low Level
tRPLZ
10
Enable Time to High Level
tRPZH
15
Enable Time to Low Level
tRPZL
15
Unit Test Conditions/Comments
Mbps
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
100 MHz clock input4 (see Figure 26)
200 Mbps 215 − 1 PRBS input6 (see Figure 29)
See Figure 25, Figure 28
See Figure 25, Figure 28
See Figure 25, Figure 28
See Figure 25, Figure 28
ns CL = 15 pF (see Figure 30, Figure 33)
ns CL = 15 pF (see Figure 30, Figure 33)
CL = 15 pF (see Figure 30, Figure 33)
ps
ps
ns CL = 15 pF (see Figure 30, Figure 33)
ps 100 MHz clock input7 (see Figure 32)
200 Mbps 215 − 1 PRBS input8 (see Figure 35)
ps
ps
ns See Figure 31, Figure 34
ns See Figure 31, Figure 34
ns See Figure 31, Figure 34
ns See Figure 31, Figure 34
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC
and temperature, and with identical packages and test circuits.
3 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
4 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
5 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
6 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
7 |VID| = 400 mV (ADN4696E, ADN4697E), VIC = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
8 |VID| = 400 mV (ADN4696E, ADN4697E), VIC = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
Rev. B | Page 5 of 20
5 Page 
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
A/Y 3.32kΩ
DI
VOD
49.9Ω
+
B/Z
3.32kΩ
VTEST –1V TO +3.4V
–
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS
Figure 19. Driver Voltage Measurement over Common-Mode Range
VCC
A/Y
DI
S1
B/Z
IOS
S2
–1V OR +3.4V
VTEST
Figure 22. Driver Short Circuit
A/Y
DI
B/Z
C1 R1
1pF 24.9Ω
R2
24.9Ω
C2
1pF
C3
2.5pF VOC
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
Figure 20. Driver Common-Mode Output Voltage Measurement
VCC
S1
A/Y
DE B/Z
S2
VA(O), VB(O),
VY(O) OR VZ(O)
R1
1.62kΩ
±1%
A/Y ≈ 1.3V
B/Z ≈ 0.7V
VOC
VOC(PP)
ΔVOC(SS)
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE; tR, tF ≤ 1ns.
2. VOC(PP) MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 23. Driver Common-Mode Output Voltage (Steady State)
Figure 21. Maximum Steady-State Output Voltage Measurement
Rev. B | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADN4691E.PDF ] | |
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