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PDF NJU26904 Data sheet ( Hoja de datos )
| Número de pieza | NJU26904 | |
| Descripción | Digital Audio Delay | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJU26904
Digital Audio Delay
■ General Description
The NJU26904 offers digital audio delay.
The NJU26904 has internal delay memory. Delay function can adjust output
time of a six-channel signal.
This delay functions are suitable for delay time adjustment such as Audio
products and time alignment such as Car Audio.
■Package
■ FEATURES
NJU26904V-C2
• 6-channel Digital Audio Delay
Delay Time 84msec for monaural channel, 42msec for stereo channel at Fs=96kHz
Delay Time 169msec for monaural channel, 85msec for stereo channel at Fs=48kHz
Delay Time 254msec for monaural channel, 127msec for stereo channel at Fs=32kHz
• Delay data width is 24 bits.
Digital Audio Format: I2S 24bit, Left-Justified, Right-Justified, BCK: 32/64fs
• Adjustable Delay Time with 1sample units for 8,121 samples at maximum.
• Selectable input sources for each channel output freely.
• To make long delay time, the NJU26904 can be connected serially.
• Non-Audio Format is possible.
- Hardware
• Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Digital Audio Format
: I2S 24bit, Left- Justified, Right-Justified, BCK : 32/64fs
• Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
• Host Interface
: I2C bus (Fast-mode/400kbps)
• Power Supply
: 3.3V
• Input terminal
: 5V Input tolerant
• Package
: SSOP24-C2 (Pb-Free)
Ver.2008-12-02
-1-
1 page  
NJU26904
■ Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Parameter
Symbol
( VSS=0V=GND, Ta=25°C )
Rating
Units
Supply Voltage *
Supply Voltage Bypass *
In
I/O, OD
Pin Voltage *
Out
VDD
VREGO
Vx(IN)
Vx(I/O) ,Vx(OD)
Vx(OUT)
-0.3 to 4.2
-0.3 to 2.3
-0.3 to 5.5 (VDD≥ 3.0V)
-0.3 to 4.2 (VDD< 3.0V)
-0.3 to 4.2
V
V
V
CLK
CLKOUT
Vx(CLK)
Vx(CLKOUT)
-0.3 to 4.2
Power Dissipation
Operating Voltage
Storage Temperature
PD
TOPR
TSTR
565
-40 to 85
-40 to 125
mW
°C
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* VDD
* VREGO
* Vx(IN)
* Vx(OD)
* Vx(I/O)
* Vx(OUT)
* Vx(CLK)
* Vx(CLKOUT)
: 8 pin
: 12 pin
: 1, 4, 5, 6, 10, 15, 23, 24 pin
: 22 pin
: 2, 3, 7, 16, 17, 18 pin
: 19, 20, 21 pin
: 14 pin
: 13 pin
■ Terminal equivalent circuit diagram
VDD
VDD(1.8V)
CLK
CLKOUT
VDD
VDD(1.8V)
PAD
RPD
Input, I/O (Input part) VSS
(1 to 7, 22, 23pin)
(With RPU: 18pin With RPD: 15, 16, 17, 24pin)
VDD
RPU
PAD
CLK/CLKOUT
(13, 14pin)
VSS
VDD
PAD
Output Disable
VSS
Output, I/O (Output part)
(2, 3, 7, 16, 17, 19, 20, 21pin )
( Open Drain Output with RPU: 18pin)
( Open Drain Output: 22pin )
STBYb
(10pin)
VSS
Fig.4 NJU26904 Terminal equivalent circuit diagram
Ver.2008-12-02
-5-
5 Page 
NJU26904
3. Digital Audio Interface
3.1 Digital Audio Data Format
The NJU26904 can use three kinds of formats hereafter as industry-standard digital audio data format.
(1) I2S
: MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing)
(2) Left-Justified : LR clock -- MSB is placed for changing.
(3) Right-Justified: LSB is placed just before LR clock change rate.
The main differences among three kinds of formats are in the position relation between LR clock (LR) and
an audio data (SDI, SDO).
- In every format:
: a left channel is transmitted previously.
- In Right/Left-Justified : LR clock ='High' shows a left channel.
- I2S : LR clock=”Low” shows a left channel.
- The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than
the number of sum total transmission bits of a L/R channel is needed at least.
- One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes
equal to a sample rate (Fs).
- The NJU26904 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks.
This serial data format is applied to both MASTER and SLAVE mode.
3.2 Serial Audio Data Input/output
The NJU26904 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output
lines: SDO0, SDO1 and SDO2. (Table 9).
Table 8 Serial Audio Input Pin Description
Pin No. Symbol
Description
6 SDI0 Audio Data Input 0 L/R
5 SDI1 Audio Data Input 1 L/R
4 SDI2 Audio Data Input 2 L/R
Table 9 Serial Audio Output Pin Description
Pin No. Symbol
Description
19 SDO0 Audio Data Output 0 L/R
20 SDO1 Audio Data Output 1 L/R
21 SDO2 Audio Data Output 2 L/R
The input terminal is selectable for the output terminal freely.
Refer to Figure 2 NJU26904 Function Diagram.
Ver.2008-12-02
- 11 -
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NJU26904.PDF ] | |
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