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PDF CAT24C44 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C44 | |
| Descripción | 256-Bit Serial Nonvolatile CMOS Static RAM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24C44
256-Bit Serial Nonvolatile CMOS Static RAM
FEATURES
s Single 5V Supply
s Infinite E2PROM to RAM Recall
s CMOS and TTL Compatible I/O
s Low CMOS Power Consumption:
–Active: 3 mA Max.
–Standby: 30 µA Max.
s Power Up/Down Protection
s 10 Year Data Retention
s JEDEC Standard Pinouts:
–8-pin DIP
–8-pin SOIC
s 100,000 Program/Erase Cycles (E2PROM)
s Auto Recall on Power-up
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile E2PROM array which allows for easy trans-
fer of data from RAM array to E2PROM (STORE) and
from E2PROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlimited
RAM write operations either through external RAM
writes or internal recalls from E2PROM. Internal false
store protection circuitry prohibits STORE operations
when VCC is less than 3.5V (typical) ensuring E2PROM
data integrity.
The CAT24C44 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles (E2PROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-pin plastic DIP and SOIC pack-
ages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (S)
CE 1
SK 2
DI 3
DO 4
8 VCC
CE 1
7 STORE SK 2
6 RECALL DI 3
5 VSS
DO 4
8 VCC
7 STORE
6 RECALL
5 VSS
5157 FHD F01
PIN FUNCTIONS
Pin Name
SK
DI
DO
CE
RECALL
STORE
VCC
VSS
Function
Serial Clock
Serial Input
Serial Data Output
Chip Enable
Recall
Store
+5V
Ground
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25019-0A 2/98 N-1
1 page  
CAT24C44
DEVICE OPERATION
The CAT24C44 is intended for use with standard micro-
processors. The CAT24C44 is organized as 16 registers
by 16 bits. Seven 8-bit instructions control the device’s
operating modes, the RAM reading and writing, and the
E2PROM storing and recalling. It is also possible to
control the E2PROM store and recall functions in hard-
ware with the STORE and RECALL pins. The CAT24C44
operates on a single 5V supply and will generate, on
chip, the high voltage required during a RAM to E2PROM
storing operation.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The CE (Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical ‘1’ start bit, 4 address bits (data read or write
operations) or 4 “Don’t Care” bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
from the device: If the CE pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed, and the shift register internal to the CAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1–D15) are timed from the rising
edge of the clock.
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location speci-
fied. The CE pin must remain high during the entire write
operation.
Figure 1. RAM Read Cycle Timing
CE
1 2 3 4 5 6 7 8 9 10 11 12
SK
22 23 24
(18)
DI
1 A A A A1
1X
HIGH-Z
DO
D0 D1 D2 D3
Figure 2. RAM Write Cycle Timing
CE
1 2 3 4 5 6 7 8 9 10 11 12
SK
D14 D15 D0
5157 FHD F02
22 23 24
DI
1A A A A
0
11
D0 D1 D2 D3
Note:
(1) Bit 8 of READ instruction is “Don’t Care”.
5
D13 D14 D15
5157 FHD F03
Doc. No. 25019-0A 2/98 N-1
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CAT24C44.PDF ] | |
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