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PDF ADAS1000-2 Data sheet ( Hoja de datos )
| Número de pieza | ADAS1000-2 | |
| Descripción | Five Electrode Electrocardiogram (ECG) Analog Front End | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Power, Five Electrode
Electrocardiogram (ECG) Analog Front End
ADAS1000/ADAS1000-1/ADAS1000-2
FEATURES
Biopotential signals in; digitized signals out
5 acquisition (ECG) channels and one driven lead
Parallel ICs for up to 10+ electrode measurements
Master ADAS1000 or ADAS1000-1 used with slave
ADAS1000-2
AC and dc lead-off detection
Internal pace detection algorithm on 3 leads
Support for user’s own pace
Thoracic impedance measurement (internal/external path)
Selectable reference lead
Scalable noise vs. power control, power-down modes
Low power operation from
11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes)
Lead or electrode data available
Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38
R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005,
IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0
b:2005, IEC60601-2-51 ed. 1.0 b: 2005
Fast overload recovery
Low or high speed data output rates
Serial interface SPI-/QSPI™-/DSP-compatible
56-lead LFCSP package (9 mm × 9 mm)
64-lead LQFP package (10 mm × 10 mm body size)
APPLICATIONS
ECG: monitor and diagnostic
Bedside patient monitoring, portable telemetry, Holter,
AED, cardiac defibrillators, ambulatory monitors, pace
maker programmer, patient transport, stress testing
GENERAL DESCRIPTION
The ADAS1000/ADAS1000-1/ADAS1000-2 measure electro
cardiac (ECG) signals, thoracic impedance, pacing artifacts,
and lead-on/lead-off status and output this information in the
form of a data frame supplying either lead/vector or electrode
data at programmable data rates. Its low power and small size
make it suitable for portable, battery-powered applications.
The high performance also makes it suitable for higher end
diagnostic machines.
The ADAS1000 is a full-featured, 5-channel ECG including
respiration and pace detection, while the ADAS1000-1 offers
only ECG channels with no respiration or pace features. Similarly,
the ADAS1000-2 is a subset of the main device and is configured
for gang purposes with only the ECG channels enabled (no
respiration, pace, or right leg drive).
The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to
simplify the task of acquiring and ensuring quality ECG signals.
They provide a low power, small data acquisition system for
biopotential applications. Auxiliary features that aid in better
quality ECG signal acquisition include multichannel averaged
driven lead, selectable reference drive, fast overload recovery,
flexible respiration circuitry returning magnitude and phase
information, internal pace detection algorithm operating on
three leads, and the option of ac or dc lead-off detection. Several
digital output options ensure flexibility when monitoring and
analyzing signals. Value-added cardiac post processing is
executed externally on a DSP, microprocessor, or FPGA.
Because ECG systems span different applications, the
ADAS1000/ADAS1000-1/ADAS1000-2 feature a power/noise
scaling architecture where the noise can be reduced at the
expense of increasing power consumption. Signal acquisition
channels can be shut down to save power. Data rates can be
reduced to save power.
To ease manufacturing tests and development as well as offer
holistic power-up testing, the ADAS1000/ADAS1000-1/
ADAS1000-2 offer a suite of features, such as dc and ac test
excitation via the calibration DAC and cyclic redundancy check
(CRC) redundancy testing, in addition to readback of all
relevant register address space.
The input structure is a differential amplifier input, thereby
allowing users a variety of configuration options to best suit
their application.
The ADAS1000/ADAS1000-1/ADAS1000-2 are available in two
package options, a 56-lead LFCSP package and a 64-lead LQFP
package. Both packages are specified over a −40°C to +85°C
temperature range.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
SPECIFICATIONS
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA =
−40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external
regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%.
Front-end gain settings: GAIN 0 = ×1.4, GAIN 1 = ×2.1, GAIN 2 = ×2.8, GAIN 3 = ×4.2.
Table 2.
Parameter
ECG CHANNEL
Electrode Input Range
Input Bias Current
Input Offset
Min
0.3
0.63
0.8
0.97
−40
−200
Input Offset Tempco1
Input Amplifier Input
Impedance2
CMRR2
Crosstalk1
Resolution2
105
Integral Nonlinearity Error
Differential Nonlinearity Error
Gain2
GAIN 0 (×1.4)
GAIN 1 (×2.1)
GAIN 2 (×2.8)
GAIN 3 (×4.2)
Gain Error
−1
−2
Typ Max
1.3
1.3
1.3
1.3
±1
−7
−7
−15
−22
±2
1||10
110
80
19
18
16
30
5
4.9
9.81
39.24
3.27
6.54
26.15
2.45
4.9
19.62
1.63
3.27
13.08
+0.01
+0.1
2.3
1.97
1.8
1.63
+40
+200
+1
+2
Unit
V
V
V
V
nA
nA
mV
mV
mV
mV
μV/°C
GΩ||pF
dB
dB
Bits
Bits
Bits
ppm
ppm
µV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
%
%
Test Conditions/Comments
These specifications apply to the following pins:
ECG1_LA, ECG2_LL, ECG3_RA, ECG4_V1, ECG5_V2,
CM_IN (CE mode), EXT_RESP_xx pins when used in
extend switch mode
Independent of supply
GAIN 0 (gain setting ×1.4)
GAIN 1 (gain setting ×2.1)
GAIN 2 (gain setting ×2.8)
GAIN 3 (gain setting ×4.2)
Relates to each electrode input; over operating range;
dc and ac lead-off are disabled
AGND to AVDD
Electrode/vector mode with VCM = VCM_REF GAIN 3
GAIN 2
GAIN 1
GAIN 0
At 10 Hz
51 kΩ imbalance, 60 Hz with ±300 mV differential dc
offset; per AAMI/IEC standards; with driven leg loop closed
Between channels
Electrode/vector mode, 2 kHz data rate, 24-bit data-word
Electrode/vector mode, 16 kHz data rate, 24-bit data-word
Electrode/analog lead mode, 128 kHz data rate, 16-bit
data-word
GAIN 0; all data rates
GAIN 0
Referred to input. (2 × VREF)/Gain/(2N − 1); applies after
factory calibration; user calibration adjusts this number
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
No factory calibration for this gain setting
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
GAIN 0 to GAIN 2, factory calibrated; programmable
user or factory calibration option enables; factory gain
calibration applies only to standard ECG interface
GAIN 3 setting, no factory calibration for this gain
Rev. B | Page 5 of 80
5 Page 
Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
tDRDY_CS
DRDY
SCLK
tCSHA
tCSSA
tCH
tCL
tCSHD
tCSSD
CS
SDI
SDO
MSB
tDS
tDH
DB[31]
N
DB[30]
N
DB[29]
N
DB[25]
N
DB[24]
N
DB[23] DB[1]
LSB
DB[0]
N
tCSW
MSB
DB[31]
N+1
DB[30]
N+1
LSB
DB[1] DB[0]
N+1 N+1
tCSO
R/W ADDRESS = 0x40 (FRAMES)
DATA
DATA = NOP or 0x40
MSB
DRDY
DB[31]
N–1
DB[30]
N–1
DB[25] DB[24] DB[23] DB[1]
N–1 N–1 N–1 N–1
LSB
DB[0]
N–1
MSB
DB[31]
N
DB[30]
N
DB[1]
N
LSB
DB[0]
N
tDO
PREVIOUS DATA
HEADER (FIRST WORD OF FRAME)
Figure 3. Starting Read Frame Data (CPHA = 1, CPOL = 1)
SCLK
CS
SDI
tCH
tCSHA
tCSSA
tCL
tDS
MSB
DB[31]
tDH
DB[30]
DB[29]
DB[28]
DB[24]
DB[2]
tCSHD
tCSSD
DB[1]
LSB
DB[0]
tCSW
SDO
R/W
tDO
MSB
ADDRESS
DO_31LAST DO_30LAST DO_29LAST DO_28LAST
DATA
LSB
DO_1LAST DO_0LAST
tDO
Figure 4. Data Read and Write Timing Diagram (CPHA = 0, CPOL = 0)
Rev. B | Page 11 of 80
11 Page | ||
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| PDF Descargar | [ Datasheet ADAS1000-2.PDF ] | |
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