|
|
PDF AD9518-1 Data sheet ( Hoja de datos )
| Número de pieza | AD9518-1 | |
| Descripción | 6-Output Clock Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9518-1 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.30 GHz to 2.65 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9518-11 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to
2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9518-1 emphasizes low jitter and phase noise to maximize
data converter performance, and it can benefit other applications
with demanding phase noise and jitter requirements.
The AD9518-1 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
For applications that require additional outputs, a crystal
reference input, zero-delay, or EEPROM for automatic
configuration at startup, the AD9520 and AD9522 are available.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
6-Output Clock Generator with
Integrated 2.5 GHz VCO
AD9518-1
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
LVPECL
LVPECL
LVPECL
AD9518-1
Figure 1.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
In addition, the AD9516 and AD9517 are similar to the AD9518
but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32.
The AD9518-1 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated by
connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-1 is specified for operation over the industrial
range of −40°C to +85°C.
1 AD9518 is used throughout the data sheet to refer to all the members of the
AD9518 family. However, when AD9518-1 is used, it refers to that specific
member of the AD9518 family.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9518-1
Parameter
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
Min
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Typ Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
PLL DIGITAL LOCK DETECT WINDOW2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
CPV is CP pin voltage; VCP is charge pump power supply voltage
Programmable
mA With CPRSET = 5.1 kΩ
mA
% CPV = VCP/2 V
kΩ
nA
% 0.5 < CPV < VCP − 0.5 V
% 0.5 < CPV < VCP − 0.5 V
% CPV = VCP/2 V
See the VCXO/VCO Feedback Divider N—P, A, B, R section
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz A, B counter input frequency (prescaler input frequency divided
by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0] (see Table 44)
ps
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20 log(N) (where N is the value of the N divider)
Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an approxi-
mation of the PFD/CP in-band phase noise (in the flat region) inside
the PLL loop bandwidth; when running closed-loop, the phase
noise, as observed at the VCO output, is increased by 20 log(N)
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. C | Page 5 of 64
5 Page 
Data Sheet
AD9518-1
LD, STATUS, AND REFMON PINS
Table 15.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage High (VOH)
Output Voltage Low (VOL)
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range (REF1 and REF2 Only)
LD PIN COMPARATOR
Trip Point
Hysteresis
Min Typ Max Unit
2.7 V
0.4 V
100 MHz
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 44, Register 0x017, Register 0x01A, and
Register 0x01B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
3 pF On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
1.02 MHz Frequency above which the monitor always indicates the
presence of the reference
8 kHz Frequency above which the monitor always indicates the
presence of the reference
1.6 V
260 mV
POWER DISSIPATION
Table 16.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
Min Typ Max Unit Test Conditions/Comments
0.76 1.0 W
No clock; no programming; default register values;
does not include power dissipated in external resistors
1.1 1.7 W
PLL on; internal VCO = 2476 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 619 MHz;
does not include power dissipated in external resistors
75 185 mW PD pin pulled low; does not include power dissipated
in terminations
31 mW PD pin pulled low; PLL power-down, Register 0x010[1:0] =
01b; SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
4 4.8 mW PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
30 mW VCO divider bypassed
20 mW All references off to differential reference enabled
4 mW All references off to REF1 or REF2 enabled; differential
reference not enabled
70 mW CLK input selected to VCO selected
75 mW PLL off to PLL on, normal operation; no reference
enabled
30 mW Divider bypassed to divide-by-2 to divide-by-32
160 mW No LVPECL output on to one LVPECL output on,
independent of frequency
90 mW Second LVPECL output turned on, same channel
Rev. C | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9518-1.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9518-0 | 6-Output Clock Generator | Analog Devices |
| AD9518-1 | 6-Output Clock Generator | Analog Devices |
| AD9518-2 | 6-Output Clock Generator | Analog Devices |
| AD9518-3 | 6-Output Clock Generator | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |