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PDF AD9523-1 Data sheet ( Hoja de datos )
| Número de pieza | AD9523-1 | |
| Descripción | Low Jitter Clock Generator | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Jitter Clock Generator with
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9523-1
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
Dual VCO dividers
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <150 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Broadband timing jitter: 124 fs
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC_IN, OSC_IN
AD9523-1
PLL1
PLL2
DIVIDE-BY-
3, 4, 5
8 OUTPUTS
OUT0,
OUT0
OUT3,
OUT3
OUT10,
OUT10
OUT13,
OUT13
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
DIVIDE-BY-
3, 4, 5
ZERO
DELAY
EEPROM
6 OUTPUTS
14-CLOCK
DISTRIBUTION
ZD_IN, ZD_IN
Figure 1.
OUT4,
OUT4
OUT9,
OUT9
GENERAL DESCRIPTION
The AD9523-1 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO with two VCO dividers. The on-chip VCO
tunes from 2.94 GHz to 3.1 GHz.
The AD9523-1 is designed to support the clock requirements
for long term evolution (LTE) and multicarrier GSM base
station designs. It relies on an external VCXO to provide the
reference jitter cleanup to achieve the restrictive low phase noise
requirements necessary for acceptable data converter SNR
performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free, coarse timing adjustment
in increments that are equal to half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9523-1
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 2949.12 MHz, doubler is on, unless otherwise noted.
Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and
TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
AMBIENT TEMPERATURE RANGE, TA
JUNCTION TEMPERATURE, TJ
Min Typ
3.135
3.135
3.135
3.135
1.768
−40
3.3
3.3
3.3
3.3
1.8
+25
Max Unit Test Conditions/Comments
3.465
3.465
3.465
3.465
1.832
+85
+115
V
V
V
V
V
°C
°C
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
1.8 V ± 5%
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO and VCO Divider M1
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VCO Divider M1 Enabled
LVPECL Mode, LVDS Mode
Min
HSTL Mode, CMOS Mode
VCO Divider M2 Enabled
LVPECL Mode, LVDS Mode
HSTL Mode, CMOS Mode
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
Typ Max
37 41.9
70 75.8
4 5.1
3 3.6
26 30.1
24.5 28.6
3.2 5.8
6.4 12
11.5 13.2
40 45
6.5 7.5
23 26.3
13 14.4
41 46.5
Unit Test Conditions/Comments
mA Decreases by 9 mA typical if REFB is turned off
mA All outputs use VCO Divider M1
mA Use VCO Divider M1; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
mA Use VCO Divider M1; values are independent
of the number of outputs turned on
mA Use VCO Divider M2; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
mA Use VCO Divider M2; values are independent
of the number of outputs turned on
mA Current for each divider: f = 122.88 MHz
mA Current for each divider: f = 983.04 MHz
Channel x control register, Bit 4 = 0
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
Rev. C | Page 4 of 63
5 Page 
AD9523-1
Data Sheet
JITTER AND NOISE CHARACTERISTICS
Table 10.
Parameter
OUTPUT ABSOLUTE RMS TIME JITTER
Min Typ
LVPECL Mode, HSTL Mode, LVDS Mode
109
115
150
177
187
124
Max Unit
fs
fs
fs
fs
fs
fs
Test Conditions/Comments
Application example based on a typical setup (see Table 3);
f = 122.88 MHz
Integrated BW = 200 kHz to 5 MHz
Integrated BW = 200 kHz to 10 MHz
Integrated BW = 12 kHz to 20 MHz
Integrated BW = 10 kHz to 61 MHz
Integrated BW = 1 kHz to 61 MHz
Integrated BW = 1 MHz to 61 MHz
PLL2 CHARACTERISTICS
Table 11.
Parameter
VCO (ON CHIP)
Frequency Range
Gain
PLL2 FIGURE OF MERIT (FOM)
MAXIMUM PFD FREQUENCY
Antibacklash Pulse Width
Minimum
Low
High
Maximum
Min Typ Max Unit Test Conditions/Comments
2940
45
−226
3100
MHz
MHz/V
dBc/Hz
259 MHz
200 MHz
135 MHz
80 MHz
High is the initial PLL2 antibacklash pulse width setting.
The user must program Register 0x019[4] = 1b to enable SPI
control of the antibacklash pulse width to the setting defined
in Register 0x00F2[3:2] and Table 46.
LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL
Table 12.
Parameter
VOLTAGE
Input High
Input Low
INPUT LOW CURRENT
CAPACITANCE
RESET TIMING
Pulse Width Low
Inactive to Start of Register
Programming
SYNC TIMING
Pulse Width Low
Min Typ Max Unit
2.0 V
0.8 V
±80 ±250 µA
3 pF
50 ns
100 ns
Test Conditions/Comments
The minus sign indicates that, due to the internal pull-up
resistor, current is flowing out of the AD9523-1
1.5 ns High speed clock is the CLK input signal
Rev. C | Page 10 of 63
11 Page | ||
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