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PDF AD9528 Data sheet ( Hoja de datos )
| Número de pieza | AD9528 | |
| Descripción | JESD204B Clock Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
14 outputs configurable for HSTL or LVDS
Maximum output frequency
2 outputs up to 1.25 GHz
12 outputs up to 1 GHz
Dependent on the voltage controlled crystal oscillator
(VCXO) frequency accuracy (start-up frequency accuracy:
<±100 ppm)
Dedicated 8-bit dividers on each output
Coarse delay: 63 steps at 1/2 the period of the RF VCO
divider output frequency with no jitter impact
Fine delay: 15 steps of 31 ps resolution
Typical output to output skew: 20 ps
Duty cycle correction for odd divider settings
Output 12 and Output 13, VCXO output at power up
Absolute output jitter: <160 fs at 122.88 MHz, 12 kHz to
20 MHz integration range
Digital frequency lock detect
SPI- and I2C-compatible serial control port
Dual PLL architecture
PLL1
Provides reference input clock cleanup with external VCXO
Phase detector rate up to 110 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVDS/HSTL outputs from VCXO used for radio
frequency/intermediate frequency (RF/IF) synthesizers
PLL2
Phase detector rate of up to 275 MHz
Integrated low noise VCO
APPLICATIONS
High performance wireless transceivers
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs;
supports JESD204B
Low jitter, low phase noise clock distribution
ATE and high performance instrumentation
JESD204B Clock Generator with
14 LVDS/HSTL Outputs
AD9528
FUNCTIONAL BLOCK DIAGRAM
VXCO_IN
REFA
REFB
REF_SEL
PLL1
PLL2
SYSREF_REQ
SYSREF
JESD204B
֯
֯
OUT0/
OUT0
OUT13/
OUT13
CONTROL
INTERFACE
(SPI AND I2C)
AD9528
CLOCK
DISTRIBUTION
14 OUTPUTS
Figure 1.
GENERAL DESCRIPTION
The AD9528 is a two-stage PLL with an integrated JESD204B
SYSREF generator for multiple device synchronization. The first
stage phase-locked loop (PLL) (PLL1) provides input reference
conditioning by reducing the jitter present on a system clock.
The second stage PLL (PLL2) provides high frequency clocks
that achieve low integrated jitter as well as low broadband noise
from the clock output drivers. The external VCXO provides the
low noise reference required by PLL2 to achieve the restrictive
phase noise and jitter requirements necessary to achieve acceptable
performance. The on-chip VCO tunes from 3.450 GHz to
4.025 GHz. The integrated SYSREF generator outputs single
shot, N-shot, or continuous signals synchronous to the PLL1
and PLL2 outputs to time align multiple devices.
The AD9528 generates two outputs (Output 1 and Output 2)
with a maximum frequency of 1.25 GHz, and 12 outputs up to
1 GHz. Each output can be configured to output directly from
PLL1, PLL2, or the internal SYSREF generator. Each of the 14
output channels contains a divider with coarse digital phase
adjustment and an analog fine phase delay block that allows
complete flexibility in timing alignment across all 14 outputs.
The AD9528 can also be used as a dual input flexible buffer to
distribute 14 device clock and/or SYSREF signals. At power-up,
the AD9528 sends the VCXO signal directly to Output 12 and
Output 13 to serve as the power-up ready clocks.
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function where applicable.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9528
Data Sheet
SPECIFICATIONS
The AD9528 is configured for dual loop mode. The REFA differential input is enabled at 122.88 MHz, fVCXO = 122.88 MHz and single-
ended, fVCO = 3686.4 MHz, VCO divider = 3. Doubler and analog delay are off, SYSREF generation is on, unless otherwise noted. Typical
is given for VDDx = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDDx
and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDDx1
TEMPERATURE
Ambient Temperature
Range, TA
Junction Temperature, TJ
Min Typ Max Unit Test Conditions/Comments
3.135 3.3 3.465 V
3.3 V ± 5%
−40 +25 +85 °C
+115 °C
Refer to the Power Dissipation and Thermal Considerations section to
calculate the junction temperature
1 VDDx includes the VDD pins (Pin 1, Pin 10, Pin 16, Pin 20, and Pin 72) and the VDD13 pin through the VDD0 pin, unless otherwise noted. See the Pin Configuration and Function
Descriptions for details.
SUPPLY CURRENT
Table 2.
Parameter
SUPPLY CURRENT
Dual Loop Mode
VDD (Pin 1, Pin 72)
VDD (Pin 10)
VDD (Pin 16)
VDD ( Pin 20)
Single Loop Mode
VDD (Pin 1, Pin 72)
VDD (Pin 10)
VDD (Pin 16)
VDD (Pin 20)
Buffer Mode
VDD (Pin 1, Pin 72)
VDD (Pin 10)
VDD (Pin 16)
VDD (Pin 20)
Chip Power-Down
Mode
VDD (Pin 1, Pin 10,
Pin 16, Pin 20,
and Pin 72)
Min Typ Max Unit Test Conditions/Comments
Excludes clock distribution section; clock distribution outputs running as follows:
7 HSTL device clocks at 122.88 MHz, 7 LVDS SYSREF clocks (3.5 mA) at 960 kHz
PLL1 and PLL2 enabled
19 21 mA
29 32 mA
34 37 mA
64 71 mA
PLL1 off and REFA and REFB inputs off
7 9 mA 122.88 MHz reference source applied to the VCXO inputs (input to PLL2)
29 32 mA
34 37 mA
64 71 mA
PLL1 and PLL2 off, REFA and REFB inputs disabled; 122.88 MHz reference source
applied to VCXO differential inputs to drive 7 of 14 outputs, internal SYSREF
generator off, 960 kHz input source applied to SYSREF differential inputs to drive
the other 7 outputs, dividers in clock distribution path bypassed in clock
distribution channel
17 19 mA
23 25 mA
2 3 mA
15 19 mA
15 mA Chip power-down bit enabled (Register 0x0500, Bit 0 = 1)
Rev. C | Page 4 of 67
5 Page 
AD9528
Data Sheet
Parameter
fOUT = 1228.8 MHz
10 Hz Offset
100 Hz Offset
1 kHz Offset
10 kHz Offset
100 kHz Offset
800 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
LVDS OUTPUT
fOUT = 122.88 MHz
10 Hz Offset
100 Hz Offset
1 kHz Offset
10 kHz Offset
100 kHz Offset
800 kHz Offset
1 MHz Offset
10 MHz Offset
40 MHz Offset
fOUT = 1228.8 MHz
10 Hz Offset
100 Hz Offset
1 kHz Offset
10 kHz Offset
100 kHz Offset
800 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
Min Typ Max Unit
−85
−95
−103
−114
−120
−126
−128
−147
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
OUT1 and OUT2 only, channel divider = 1
−111
−113
−123
−135
−140
−147
−148
−157
−157
−85
−95
−103
−114
−120
−126
−128
−146
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
OUT1 and OUT2 only, channel divider = 1
CLOCK OUTPUT ABSOLUTE TIME JITTER
Table 13.
Parameter
OUTPUT ABSOLUTE RMS TIME JITTER
Min Typ
Dual Loop Mode
HSTL Output
fOUT = 122.88 MHz
fOUT = 1228.8 MHz, Channel
Divider = 1
117
123
159
172
177
109
114
116
147
154
160
74
Max Unit
Test Conditions/Comments
Application examples are based on typical setups (see
Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950);
reference = 122.88 MHz; channel divider = 10 or 1;
PLL2 LBW = 450 kHz
fs Integrated BW = 200 kHz to 5 MHz
fs Integrated BW = 200 kHz to 10 MHz
fs Integrated BW = 12 kHz to 20 MHz
fs Integrated BW = 10 kHz to 40 MHz
fs Integrated BW = 1 kHz to 40 MHz
fs Integrated BW = 1 MHz to 40 MHz
fs Integrated BW = 200 kHz to 5 MHz
fs Integrated BW = 200 kHz to 10 MHz
fs Integrated BW = 12 kHz to 20 MHz
fs Integrated BW = 10 kHz to 100 MHz
fs Integrated BW = 1 kHz to 100 MHz
fs Integrated BW = 1 MHz to 100 MHz
Rev. C | Page 10 of 67
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9528.PDF ] | |
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