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PDF HMC6832 Data sheet ( Hoja de datos )
| Número de pieza | HMC6832 | |
| Descripción | 2:8 Differential Fanout Buffer | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Ultralow noise floor: −165.9 dBc/Hz or −165.2 dBc/Hz
(LVPECL or LVDS) at 2000 MHz
Configurable to LVPECL or pseudo LVDS outputs
2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only)
Wideband: 10 MHz to 3500 MHz operating frequency range
Flexible input interface
LVPECL, LVDS, CML, and CMOS compatible
AC or dc coupling
On-chip 50 kΩ pull-up/pull-down resistors to VDD and
GND
Multiple output drivers
Up to 8 differential or 16 single-ended LVPECL or LVDS
outputs
Low speed digital control via the IN_SEL and CONFIG pins
28-lead, 5 mm × 5 mm, LFCSP package, 25 mm2
APPLICATIONS
SONET, Fibre Channel, GigE clock distribution
ADC/DAC clock distribution
Low skew and jitter clocks
Wireless/wired communications
Level translation
High performance instrumentation
Medical imaging
Single-ended to differential conversions
Low Noise, 2:8 Differential
Fanout Buffer
HMC6832
GENERAL DESCRIPTION
The HMC6832 is an input selectable, 2:8 differential fanout
buffer designed for low noise clock distribution. The IN_SEL
control pin selects one of the two differential inputs. This input
is then buffered to all eight differential outputs. The low jitter
outputs of the HMC6832 lead to synchronized low noise
switching of downstream circuits, such as mixers, analog-to-
digital converters (ADCs)/digital-to-analog converters (DACs),
or serializer/deserializer (SERDES) devices. The device is capable
of low voltage, positive emitter-coupled logic (LVPECL) or low
voltage differential signaling (LVDS) configurations by pulling
the CONFIG pin low for LVPECL or high or open (internally
pulled high) for pseudo LVDS.
PRODUCT HIGHLIGHTS
1. Multiple Output Configurations.
The CONFIG pin allows the user to select LVPECL or
LVDS output termination.
2. Multiple Supply Voltage Operation.
The HMC6832 operates at 2.5 V or 3.3 V for LVPECL
terminations (2.5 V only for LVDS).
3. Low Noise.
The HMC6832 noise is low, typically from −168 dBc/Hz to
−162 dBc/Hz up to 3000 MHz.
4. Low Propagation Delay.
The HMC6832 displays a low delay, less than 207 ps,
typical. Channel skew is also low, ±5 ps, typical.
5. Low Core Current.
The HMC6832 has a low core current of 56 mA, typical.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
HMC6832
Data Sheet
SPECIFICATIONS
Typical is given as fINPUT = 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, TNOMINAL = 25°C, unless otherwise noted. All outputs
captured using 50 Ω scope termination. 50 Ω board termination on inputs used to minimize reflections.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
VDD
LVPECL
LVDS
Input Common-Mode Voltage
SELECTION PINS
IN_SEL Pin
Input Voltage Low (VIL)
Input Voltage High (VIH)
CONFIG Pin
Input Voltage Low (VIL)
Input Voltage High (VIH)
TEMPERATURE RANGE, TA
SUPPLY CURRENT
Core Current
Full Load Current
LVPECL Termination
LVDS Termination
RF INPUT CHARACTERISTICS
Operating Frequency Range
Input Swing (Single-Ended)
Input Capacitance
Pull-Up/Pull-Down Resistance
Min Typ Max Unit Test Conditions/Comments
2.375
3.0
2.375
GND + 0.2
2.5
3.3
2.5
VDD/2
VDD/2 + 0.4
2VDD/3 + 0.3
−40
+25
56
56
301
283
125
10
0.1
3.6
50
2.625
3.6
2.625
VDD − 0.2
V 2.5 V operation
V 3.3 V operation
V
V Guaranteed by design
GND = IN0, VDD = IN1
VDD/2 − 0.4
V
V
GND = LVPECL, VDD = LVDS
2VDD/3 − 0.3 V
V
+85 °C
Outputs unterminated
mA VDD = 2.5 V
mA VDD = 3.3 V
mA RTERM1 = 86 Ω, VDD = 2.5 V
mA RTERM = 150 Ω, VDD = 3.3 V
mA RTERM = 100 Ω
3500
2
MHz
V
pF
kΩ See Figure 1
1 For LVPECL termination, RTERM is the single-ended termination resistance to GND. For LVDS termination, RTERM is the differential termination resistance.
AC OUTPUT CHARACTERISTICS
Table 2.
Parameter
DIFFERENTIAL OUTPUT VOLTAGE SWING
LVPECL Termination
LVDS Termination
OUTPUT VOLTAGE, HIGH LEVEL
LVPECL Termination
LVDS Termination
OUTPUT VOLTAGE, COMMON LEVEL
LVPECL Termination
LVDS Termination
Min Typ
652
721
462
1.63
2.51
1.65
1.30
2.15
1.42
Max Unit
mV p-p
mV p-p
mV p-p
V
V
V
V
V
V
Test Conditions/Comments
Differential inputs and outputs; adjusted for impedance
mismatch and printed circuit board (PCB) losses; see Figure 40
and Figure 41 for ac measurement test circuits
RTERM = 86 Ω, VDD = 2.5 V
RTERM = 150 Ω, VDD = 3.3 V
RTERM = 100 Ω, VDD = 2.5 V
Differential inputs and outputs
RTERM = 86 Ω, VDD = 2.5 V
RTERM = 150 Ω, VDD = 3.3 V
RTERM = 100 Ω, VDD = 2.5 V
Differential inputs and outputs; see Figure 38 and Figure 39
for dc measurement test circuits
RTERM = 86 Ω, VDD = 2.5 V
RTERM = 150 Ω, VDD = 3.3 V
RTERM = 100 Ω, VDD = 2.5 V
Rev. B | Page 4 of 23
5 Page 
HMC6832
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Maximum Voltage Between VDD Pins
and EPAD
Maximum RF Power to INPx and INNx
INPx and INNx
Minimum Output Load Resistor
LVPECL (VDD = 2.5 V)
LVPECL (VDD = 3.3 V)
LVPECL Output Load Current
Input Select Voltage Range
Maximum VAC_REF Load Current
Maximum Reflow Temperature
(MSL3 Rating)
ESD Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
Rating
−0.3 V to +4 V
15 dBm, single-ended
−0.3 V to +3.6 V
75 Ω to GND
100 Ω to GND
40 mA/single-ended
output channel
−0.3 V to +3.6 V
2 mA
260°C
Class 1C
Class C4
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
Table 9. Thermal Resistance
Package Type
28-Lead LFCSP
θJC
10.6
ESD CAUTION
Unit
°C/W
Rev. B | Page 10 of 23
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet HMC6832.PDF ] | |
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