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PDF HMC905LP3E Data sheet ( Hoja de datos )
| Número de pieza | HMC905LP3E | |
| Descripción | 6 GHz LOW NOISE PROGRAMMABLE DIVIDER | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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HMC905LP3E
v01.0414
6 GHz LOW NOISE PROGRAMMABLE
DIVIDER (N = 1 to 4)
4
4-1
Typical Applications
The HMC905LP3E is ideal for:
• LO Generation with Low Noise Floor
• Software Defined Radios
• Clock Generators
• Fast Switching Synthesizers
• Military Applications
• Test Equipment
• Sensors
Functional Diagram
Features
Low Noise Floor:
-164 dBc/Hz at 10 MHz Offset for N = 4
Programmable Frequency Divider, N = 1, 2, 3 or 4
400 MHz to 6 GHz Input Frequency Range
Up to +6 dBm Output Power
Sleep Mode: Consumes <1 µA
16 Lead 3X3 mm SMT Package: 9mm2
General Description
The HMC905LP3E is a SiGe BiCMOS low noise
programmable frequency divider in a 3x3 mm lead-
less surface mount package. The circuit can be pro-
grammed to divide from N = 1 to N = 4 in the 400 MHz
to 6 GHz input frequency range. The high level out-
put power (up to 6 dBm single ended) with a very low
SSB phase noise and 50% duty cycle makes this
device ideal for low noise clock generation, LO
generation and LO drive applications. Configurable
bias and output power controls allow current
consumption and output power control. The device
incorporates a power down feature, good input
to output isolation and fast start up time. The
HMC905LP3E can be included into fast switching
“ping-pong” applications.
Electrical Specifications, TA = +25° C, Vcc = +3.3V, Zo = 50Ω
Parameter
RF Input Characteristics
RF Input Frequency
RF Input Power
Divider Output Characteristics
Conditions
Single-ended input
Single-ended input
Min. Typ. Max.
Units
400
6000[1]
MHz
0 6 10 dBm
Output Power (Single-ended Out)
-Typically, 50 ohms load resistors connected to Vcc
- 1 bit programmable (CTRL digital signal) [2]
-2
3
6
dBm
SSB Phase Noise @ 10 kHz Offset
SSB Phase Noise @ 100 kHz Offset
SSB Phase Noise @ 10 MHz Offset
Start Up Time
+6 dBm Input Power, 6 GHz input,
Single-Ended Input and Output, Divide-by-4 [3]
EN bit from OFF to ON State (0V to Vcc)
-150
-158
-164
200
dBc/Hz
dBc/Hz
dBc/Hz
ns
Power Down Time
EN bit from ON to OFF State (Vcc to 0V)
20 ns
Setting Time at Division Ratio Change
Delay from divide ratio change
to output frequency change
25 ns
[1] Maximum 5500 MHz in Divide by 2.
[2] See typical supply currents vs. BIAS0, BIAS1, CTRL bits table
[3] See Residual Phase Noise plot
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1 page  
HMC905LP3E
v01.0414
6 GHz LOW NOISE PROGRAMMABLE
DIVIDER (N = 1 to 4)
H2, H3, H4, H5 Harmonics, Divide-by-1 [1]
0
CTRL=0,BIAS1BIAS0=00
-10
-20
H2
H3
H4
H5
-30
-40
-50
01234567
INPUT FREQUENCY (GHz)
H2, H3, H4, H5 Harmonics, Divide-by-2 [1]
0
-10
-20
-30
-40
-50 H2
H3
-60
H4
H5
-70
01234567
INPUT FREQUENCY (GHz)
4
H2, H3, H4, H5 Harmonics, Divide-by-3 [1]
0
-10
-20
-30
-40
H2
-50 H3
H4
-60 H5
-70
01234567
INPUT FREQUENCY (GHz)
H2, H3, H4, H5 Harmonics, Divide-by-4 [1]
0
-10
-20
-30
H2
-40 H3
H4
H5
-50
01234567
INPUT FREQUENCY (GHz)
Input to Output Isolation
-20
-30
-40
-50
-60
-70
-80
0123456
INPUT FREQUENCY (GHz)
7
[1] CTRL = 0, BIAS1, BIAS1 BIAS0 = 00, Pin = 6 dBm
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4-4
5 Page 
v01.0414
Evaluation PCB Schematic
HMC905LP3E
6 GHz LOW NOISE PROGRAMMABLE
DIVIDER (N = 1 to 4)
4
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4 - 10
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HMC905LP3E.PDF ] | |
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