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PDF HMC629LP4 Data sheet ( Hoja de datos )

Número de pieza HMC629LP4
Descripción 3 dB LSB GaAs MMIC 4-BIT DIGITAL ATTENUATOR
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! HMC629LP4 Hoja de datos, Descripción, Manual

v08.0112
Typical Applications
The HMC629LP4(E) is ideal for:
• Cellular/3G Infrastructure
• WiBro / WiMAX / 4G
• Microwave Radio & VSAT
• Test Equipment and Sensors
• IF & RF Applications
Functional Diagram
HMC629LP4 / 629LP4E
3 dB LSB GaAs MMIC 4-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Features
3 dB LSB Steps to 45 dB
Power-Up State Selection
Low Insertion Loss: 2.5 dB
TTL/CMOS Compatible, Serial, Parallel
or Latched Parallel Control
±0.25 dB Typical Step Error
Single +3V or +5V Supply
24 Lead 4x4mm SMT Package: 16mm2
General Description
The HMC629LP4(E) is a broadband 4-bit GaAs IC
Digital Attenuator in a low cost leadless SMT package.
This versatile digital attenuator incorporates off-chip
AC ground capacitors for near DC operation, making
it suitable for a wide variety of RF and IF applications.
The dual mode control interface is CMOS/TTL
compatible, and accepts either a three wire serial input
or a 4-bit parallel word. For applications which require
only 33 dB of attenuation range, the HMC629LP4(E)
provides excellent attenuation accuracy up to 10 GHz.
The HMC629LP4(E) is housed in a RoHS compliant
4x4 mm QFN leadless package, and requires no
external matching components.
Electrical Specifications,
TA = +25° C, 50 Ohm System, with Vdd = +5V & Vctl = 0/+5V (Unless Otherwise Noted)
Parameter
Frequency (GHz)
Min.
Typ.
Max.
Insertion Loss
DC - 6
2.5 5
Attenuation Range
Return Loss (ATTIN, ATTOUT, All Atten. States)
Attenuation Accuracy: (Referenced to Insertion Loss)
All Attenuation States
DC - 6
DC - 6
45
17
± (0.50 + 5% of Atten. Setting) Max.
Units
dB
dB
dB
dB
dB
dB
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1 page




HMC629LP4 pdf
v08.0112
HMC629LP4 / 629LP4E
3 dB LSB GaAs MMIC 4-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Parameter
Min. serial period, tSCK
Control set-up time, tCS
Control hold-time, tCH
LE setup-time, tLN
Min. LE pulse width, tLEW
Min LE pulse spacing, tLES
Serial clock hold-time from LE, tCKN
Hold Time, tPH.
Latch Enable Minimum Width, tLEN
Setup Time, tPS
Typ.
100 ns
20 ns
20 ns
10 ns
10 ns
630 ns
10 ns
0 ns
10 ns
2 ns
Timing Diagram (Latched Parallel Mode)
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)
must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in
the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired
states the LE is pulsed. See timing diagram below for reference.
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D3-D0 determines
the power-up state of the part per truth table. The
attenuator latches in the desired power-up state
approximately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Bias Voltage
Vdd (Vdc)
5
Control Voltage Table
Idd (Typ.) (mA)
2.0
State
Low
High
Vdd = +3V
0 to 0.5V @ <1 µA
2 to 3V @ <1 µA
Vdd = +5V
0 to 0.8V @ <1 µA
2 to 5V @ <1 µA
PUP Truth Table
LE
PUP1
PUP2
Attenuation State
000
45 dB
010
45 dB
001
45 dB
0 1 1 Insertion Loss
1 X X 0 to 45 dB
Note: Power-Up with LE= 1 provides direct parallel operation with
D0 - D3.
Truth Table
Control Voltage Input
D3 D2 D1 D0
Attenuation State
High
High
High
High
Reference
I.L.
High
High
High
Low
3 dB
High High Low High
6 dB
High Low High High
12 dB
Low High High High
24 dB
Any combination of the above states will provide an attenuation
approximately equal to the sum of the bits selected.
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