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PDF ADG3243 Data sheet ( Hoja de datos )
| Número de pieza | ADG3243 | |
| Descripción | Individual Control Level Translator Bus Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.5 Gbps
2.5 V/3.3 V Supply Operation
Level Translation
3.3 V to 2.5 V
2.5 V to 1.8 V
Small Signal Bandwidth 710 MHz
8-Lead SOT-23 Package
APPLICATIONS
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
2.5 V/3.3 V, 2-Bit, Individual Control
Level Translator Bus Switch
ADG3243
FUNCTIONAL BLOCK DIAGRAM
A0 B0
BE0
A1
BE1
B1
GENERAL DESCRIPTION
The ADG3243 is a 2.5 V or 3.3 V, 2-bit, 2-port digital switch
with individual channel control. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
inputs to be connected to the outputs without additional propa-
gation delay or generating additional ground bounce noise.
The switches are enabled by means of the bus enable (BEx) input
signal. This digital switch allows a bidirectional signal to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. This makes the device
suited to applications requiring level translation between different
supplies, such as converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level/voltage translation.
5. Tiny SOT-23 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADG3243
TERMINOLOGY
VCC
GND
VINH
VINL
II
IOZ
IOL
VP
RON
⌬RON
CX OFF
CX ON
CIN
ICC
⌬ICC
tPLH, tPHL
tPZH, tPZL
tPHZ, tPLZ
Max Data Rate
Channel Jitter
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
ON Resistance Match between Any Two Channels, i.e., RON max – RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of BEx.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
Extra power supply current component for the EN control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4– REV. 0
5 Page 
ADG3243
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
2.90 BSC
1.60 BSC
8765
1 234
2.80 BSC
PIN 1
1.30
1.15
0.90
0.15 MAX
1.95
BSC
0.65 BSC
1.45 MAX 0.22
0.08
0.38
0.22 SEATING
PLANE
8؇
4؇
0؇
COMPLIANT TO JEDEC STANDARDS MO-178BA
0.60
0.45
0.30
–10–
REV. 0
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADG3243.PDF ] | |
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