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PDF AD7262 Data sheet ( Hoja de datos )
| Número de pieza | AD7262 | |
| Descripción | Simultaneous Sampling SAR ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
1 MSPS, 12-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
AD7262
FEATURES
Dual simultaneous sampling 12-bit, 2-channel analog-to-
digital converter (ADC)
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7262
500 kSPS for AD7262-5
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32
Device offset calibration, system gain calibration
On-chip reference: 2.5 V
−40°C to +105°C operation
High speed serial interface
SPI/QSPI™/MICROWIRE/DSP compatible
48-lead LFCSP and LQFP
GENERAL DESCRIPTION
The AD7262/AD7262-5 are dual, 12-bit, high speed, low power,
successive approximation ADCs that operate from a single 5 V
power supply. The AD7262 features throughput rates of up to
1 MSPS per on-chip ADC. The AD7262-5 features throughput
rates of up to 500 kSPS. Two complete ADC functions allow
simultaneous sampling and conversion of two channels. Each
ADC is preceded by a true differential analog input with a PGA.
There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12,
×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7262/AD7262-5 contain four comparators. Comparator A
and Comparator B are optimized for low power, while Compara-
tor C and Comparator D have fast propagation delays. The
AD7262/AD7262-5 feature a calibration function to remove any
device offset error and programmable gain adjust registers to allow
for input path (for example, sensor) offset and gain compensation.
The AD7262/AD7262-5 have an on-chip 2.5 V reference that
can be disabled if an external referenceis preferred.
The AD7262/AD7262-5 are ideally suited for monitoring small
amplitude signals from a variety of sensors. They include all the
functionality needed for monitoring theposition feedbacksignals
from a variety of analog encoders used in motor control systems.
FUNCTIONAL BLOCK DIAGRAM
AVCC
VREFA
REF BUF
AD7262
12-BIT
VA+
VA–
PGA
T/H
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
DOUTA
CONTROL
LOGIC
VB+
VB–
VREFB
CA_CBVCC
CA+
CA–
CB+
CB–
CA_CB_GND
CC_CDVCC
CC+
CC–
CD+
CD–
CC_CD_GND
PGA
12-BIT
T/H
SUCCESSIVE
OUTPUT
APPROXIMATION DRIVERS
ADC
BUF
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
VDRIVE
DOUTB
PD0/DIN
PD1
PD2
COUTA
COUTB
COUTC
COUTD
AGND
Figure 1.
DGND
PRODUCT HIGHLIGHTS
1. Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
2. Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC for
the AD7262. The conversion results of both ADCs are
simultaneously available on separate datalines or in succes-
sion on one data line if only oneserial port is available.
3. Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
4. Internal 2.5 V reference.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property oftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 78 1.32 9.47 00 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technica l Support
www.analog.com
1 page  
AD7262
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
COMPARATORS
Input Offset
Comparator A and Comparator B
Comparator C and Comparator D
Offset Voltage Drift
Input Common-Mode Range3
Input Capacitance3
Input Impedance3
IDD Normal Mode (Static)6
Comparator A and Comparator B
Comparator C and Comparator D
Propagation Delay Time
High to Low, tPHL
Comparator A and Comparator B
Comparator C and Comparator D
Low to High, tPLH
Comparator A and Comparator B
Comparator C and Comparator D
Delay Matching
Comparator A and Comparator B
Comparator C and Comparator D
Min Typ Max
0.7 × VDRIVE
4
0.8
±1
VDRIVE − 0.2
0.4
±1
5
Twos complement
19 × tSCLK
400
1
500
±2
±2
0.5
0 to 4
0 to 1.7
4
1
±4
±4
3
6 8.5
60
120 170
1.4 3.5
0.95
0.20 0.32
0.13
24
0.93
0.18 0.28
0.12
±250
±10
Data Sheet
Unit
V
V
µA
pF
V
V
µA
pF
Test Conditions/Comments
VIN = 0 V or VDRIVE
ns
ns
MSPS
kSPS
AD7262
AD7262-5
mV
mV
μV/°C
V
V
pF
GΩ
µA
µA
µA
µA
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
TA = 25°C to 105°C only
All comparators
CA_CBVCC = 5 V
CA_CBVCC = 2.7 V
25 pF load, COUTx = 0 V, VCM = AVCC/2,
VOVERDRIVE = 200 mV differential
CA_CBVCC = 3.3 V
CA_CBVCC = 5.25 V
CC_CDVCC = 3.3 V
CC_CDVCC = 5.25 V
VCM = AVCC/2, VOVERDRIVE = 200 mV
differential
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
VCM = AVCC 2, VOVERDRIVE = 200 mV
differential
Rev. B | Page 4 of 32
5 Page 
AD7262
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
AVCC = 5V
VDRIVE = 5V
0.4
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
PGA GAIN = 2
0.2
0
–0.2
–0.4
–0.6
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 5. Typical DNL at Gain of 2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
PGA GAIN = 2
–1.0
0 500 1000 1500
2000
2500
3000
CODE
Figure 6. Typical INL at Gain of 2
3500
4000
0
–20
–40
–60
–80
–100
AVCC = 5V
VDRIVE = 2.7V
fS = 1MSPS
TA = 25°C
fIN = 100kHz
INTERNAL REFERENCE
SNR = 73dB, THD = –82.5dB
PGA GAIN = 2
–120
–140
0
50k 100k 150k 200k 250k 300k 350k 400k 450k
FREQUENCY (Hz)
Figure 7. 3 dB Typical FFT at Gain of 2
Data Sheet
0.6
AVCC = 5V
VDRIVE = 5V
0.4
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
PGA GAIN = 32
0.2
0
–0.2
–0.4
–0.6
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. Typical DNL at Gain of 32
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
PGA GAIN = 32
–1.0
0 500 1000 1500
2000
2500
3000
CODE
Figure 9. Typical INL at Gain of 32
3500
4000
0
AVCC = 5V
VDRIVE = 5V
–20 fS = 1MSPS
TA = 25°C
fIN = 100kHz
–40 INTERNAL REFERENCE
SNR = 68.38dB, THD = –82dB
PGA GAIN = 32
–60
–80
–100
–120
–140
0
50k 100k 150k 200k 250k 300k 350k 400k 450k 500k
FREQUENCY (Hz)
Figure 10. Typical FFT at Gain of 32
Rev. B | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7262.PDF ] | |
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