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PDF ADAS3023 Data sheet ( Hoja de datos )
| Número de pieza | ADAS3023 | |
| Descripción | 16-Bit 8-Channel Simultaneous Sampling Data Acquisition System | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Bit, 8-Channel Simultaneous
Sampling Data Acquisition System
ADAS3023
FEATURES
Ease-of-use, 16-bit complete data acquisition system
Simultaneous sampling selection of 2, 4, 6, and 8 channels
Differential input voltage range: ±20.48 V maximum
High impedance 8-channel input: >500 MΩ
High input common-mode rejection: 95.0 dB
User-programmable input ranges
On-chip 4.096 V reference and buffer
No latency/pipeline delay (SAR architecture)
Serial 4-wire 1.8 V to 5 V SPI-/SPORT-compatible interface
40-lead LFCSP package (6 mm × 6 mm)
−40°C to +85°C industrial temperature range
APPLICATIONS
Multichannel data acquisition and system monitoring
Process control
Power line monitoring
Automated test equipment
Patient monitoring
Spectrum analysis
Instrumentation
GENERAL DESCRIPTION
The ADAS3023 is a complete 16-bit successive approximation-
based analog-to-digital data acquisition system. This device is
capable of simultaneously sampling up to 500 kSPS for two
channels, 250 kSPS for four channels, 167 kSPS for six chan-
nels, and 125 kSPS for eight channels manufactured on the Analog
Devices, Inc., proprietary iCMOS® high voltage industrial process
technology.
The ADAS3023 integrates eight channels of low leakage track
and hold, a programmable gain instrumentation amplifier
(PGIA) stage with a high common-mode rejection offering four
differential input ranges, a precision low drift 4.096 V reference
and buffer, and a 16-bit charge redistribution successive approxi-
mation register (SAR) analog-to-digital converter (ADC). The
ADAS3023 can resolve differential input ranges of up to ±20.48 V
when using ±15 V supplies.
DIFF TO
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
FUNCTIONAL BLOCK DIAGRAM
VDDH AVDD DVDD VIO
RESET
PD
TRACK
AND
HOLD
PGIA
LOGIC/
INTERFACE
PulSAR
ADC
ADAS3023
BUF
REF
VSSH AGND DGND REFx
Figure 1.
CNV
BUSY
CS
SCK
DIN
SDO
REFIN
The ADAS3023 simplifies design challenges by eliminating
signal buffering, level shifting, amplification and attenuation,
common-mode rejection, settling time, or any of the other
analog signal conditioning challenges, yet allows for smaller
form factor, faster time to market, and lower costs.
The ADAS3023 is factory calibrated and its operation is
specified from −40°C to +85°C.
Table 1. Typical Input Range Selection
Single-Ended Signals1
Input Range, VIN
0 V to 1 V
±1.28 V
0 V to 2.5 V
±2.56 V
0 V to 5 V
±5.12 V
0 V to 10 V
±10.24 V
1 See Figure 39 and Figure 40 in the Analog Inputs section for more
information.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADAS3023
Parameter
Dynamic Range
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
DC Common-Mode Rejection Ratio
(CMRR)
−3 dB Input Bandwidth
INTERNAL REFERENCE
REFx Pins
Output Voltage
Output Current
Temperature Drift
Line Regulation
Internal Reference
Buffer Only
REFIN Output Voltage6
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
Current Drain
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS7
Data Format
VOL
VOH
POWER SUPPLIES
VIO
AVDD
DVDD
VDDH
VSSH
Test Conditions/Comments
fIN = 1 kHz, −60 dB input
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
fIN = 1 kHz, all PGIA gains
fIN = 1 kHz, all PGIA gains
fIN = 1 kHz, all channels inactive
All channels
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
−40 dBFS
TA = 25°C
TA = 25°C
REFEN bit = 1
REFEN bit = 0, REFIN pin = 2.5V
AVDD = 5 V ± 5%
AVDD = 5 V ± 5%
TA = 25°C
CREFIN, CREF1, CREF2 = 10 µF||0.1 µF
REFEN bit = 0
REFx input, REFIN = 0 V
REFIN input (buffered)
fS = 500 kSPS
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
ISINK = +500 µA
ISOURCE = −500 µA
VDDH > input voltage + 2.5 V
VSSH < input voltage − 2.5 V
Data Sheet
Min
Typ Max
Unit1
91.0 92
90.5 91.5
88.0 89.5
86.0 87.0
−100
105
95
dB
dB
dB
dB
dB
dB
dB
95.0 dB
95.0 dB
95.0 dB
95.0 dB
8 MHz
4.088
2.495
4.000
4.096
250
±5
±1
4.104
20
4
2.5 2.505
100
4.096
2.5
100
4.104
2.505
V
µA
ppm/°C
ppm/°C
μV/V
ppm
V
ms
V
V
µA
−0.3
0.7 × VIO
−0.3
0.9 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+0.1 × VIO
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
Twos complement
0.4
VIO − 0.3
V
V
1.8
4.75
4.75
14.25
−15.75
AVDD + 0.3 V
5 5.25
V
5 5.25
V
15 15.75
V
−15 −14.25
V
Rev. A | Page 4 of 32
5 Page 
ADAS3023
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0 1
IN1 2
IN2 3
IN3 4
AGND 5
IN4 6
IN5 7
IN6 8
IN7 9
COM 10
PIN 1
INDICATOR
ADAS3023
TOP VIEW
(Not to Scale)
30 AGND
29 AGND
28 AVDD
27 DVDD
26 ACAP
25 DCAP
24 AGND
23 AGND
22 DGND
21 DGND
Data Sheet
NOTES
1. CONNECT THE EXPOSED PAD TO VSSH.
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 to 4
IN0 to IN3 AI
Input Channel 0 to Input Channel 3.
6 to 9
IN4 to IN7 AI
Input Channel 4 to Input Channel 7.
5, 14, 23, AGND
24, 29,
30, 40
P Analog Ground. Connect AGND to the system analog ground plane.
10 COM
AI IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a common
point. The maximum voltage on this pin is ±10.24 V for all PGIA gains.
11 CS
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin when
sharing the serial bus. For a dedicated and simplified ADAS3023 serial interface, tie CS to DGND or CNV.
12 DIN
DI Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is clocked
into the device on the SCK rising edges. The CFG is an internal register that is updated on the rising edge
of the next end of a conversion pulse, which coincides with the falling edge of BUSY/SDO2. The CFG
register is written into the device on the first 16 clocks after conversion. To avoid corrupting a conversion
due to digital activity on the serial bus, do not write data during a conversion.
13
RESET
DI Asynchronous Reset. A low-to-high transition resets the ADAS3023. The current conversion, if active, is
aborted and the CFG register is reset to the default state.
15 PD
DI Power-Down. A low-to-high transition powers down the ADAS3023, minimizing the device operating
current. Note that PD must be held high until the user is ready to power on the device. After powering
on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion
of one dummy conversion before the device is ready to convert. Note that the RESET pin remains low for
100 ns after the release of PD. See the Power-Down Mode section for more information.
16 SCK
DI Serial Clock Input. The DIN and SDO data sent to and from the ADAS3023 are synchronized with SCK.
17 VIO
P Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the supply of
the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
18 SDO
DO Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling
edges. The conversion results are presented on this pin in twos complement format.
19 BUSY/SDO2 DO Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin when CS is
logic high. If SDO2 is enabled when CS is brought low after the EOC, the SDO outputs the data. The
conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results
are presented on this pin in twos complement format.
20 CNV
DI Convert Input. A conversion is initiated on the rising edge of the CNV pin.
21, 22 DGND
P Digital Ground. Connect DGND to the system digital ground plane.
25 DCAP P Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 μF
and a 0.1 μF local capacitor.
26 ACAP P Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and to all
of the supporting analog circuits, except for the internal reference. Decouple this internally regulated
output (ACAP) using a 10 μF capacitor and a 0.1 μF local capacitor.
Rev. A | Page 10 of 32
11 Page | ||
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