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PDF ADP5053 Data sheet ( Hoja de datos )
| Número de pieza | ADP5053 | |
| Descripción | Integrated Power Solution | |
| Fabricantes | Analog Devices | |
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Data Sheet
Integrated Power Solution with Quad Buck
Regulators and Supervisory Circuits
ADP5053
FEATURES
Wide input voltage range: 4.5 V to 15.0 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Precision enable with 0.8 V accurate threshold
Active output discharge switch
FPWM or automatic PWM/PSM selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
UVLO, OCP, and TSD protection
Open-drain processor reset with external adjustable
threshold monitoring
Watchdog refresh input
Manual reset input
APPLICATIONS
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5053 combines four high performance buck regulators, a
supervisory circuit, a watchdog timer, and a manual reset in a
48-lead LFCSP package that meets demanding performance and
board space requirements. The device enables direct connection
to high input voltages up to 15.0 V with no preregulators.
Channel 1 and Channel 2 integrate high-sidepower MOSFET and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Combining Channel 1 and Channel 2 in a parallel configuration
can provide a single output with up to 8 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver an output current of 1.2 A.
TYPICAL APPLICATION CIRCUIT
C1
4.5V TO 15V
VREG
VDD
C0
PVIN1
C2
COMP1
EN1
SS12
PVIN2
C5
COMP2
EN2
PWRGD
PVIN3
C8
COMP3
EN3
SS34
PVIN4
C11
COMP4
EN4
WDI
MR
ADP5053
INT VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1
C3
DL1 Q1
PGND RILIM1
DL2 RILIM2
SW2
Q2
BST2
FB2
C6
L1 VOUT1
C4
VOUT2
L2
C7
CHANNEL 3
BUCK REGULATOR
(1.2A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
WATCHDOG
AND RESET
BST3
SW3
C9
FB3
PGND3
BST4
C12
SW4
FB4
PGND4
RSTO
VTH
L3 VOUT3
C10
L4
VREG
VOUT4
C13
VOUTx
EXPOSED PAD
Figure 1.
The switching frequency of the ADP5053 can be programmed
or synchronized to an external clock. The ADP5053 contains a
precision enable pin on each channel for easy power-up sequencing
or adjustable UVLO threshold.
The ADP5053 contains supervisory circuits that monitor the
voltage level. The watchdog timer can generate a reset if the
WDI pin is not toggled within a preset timeout period. Processor
reset mode or system power on/off switch mode can be selected
for manual reset functionality.
Table 1. Family Models
Model
Channels
ADP5050 Four bucks, one LDO
ADP5051 Four bucks, supervisory
ADP5052 Four bucks, one LDO
I2C Package
Yes 48-Lead LFCSP
Yes 48-Lead LFCSP
No 48-Lead LFCSP
ADP5053 Four bucks, supervisory
ADP5054 Four high current bucks
No 48-Lead LFCSP
No 48-Lead LFCSP
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property oftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 78 1.32 9.47 00 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technica l Support
www.analog.com
1 page  
ADP5053
Data Sheet
SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 2.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
UNDERVOLTAGE LOCKOUT
Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
Range
SYNC Input
Input Clock Range
Input Clock Pulse Width
Minimum On Time
Minimum Off Time
Input Clock High Voltage
Input Clock Low Voltage
SYNC Output
Clock Frequency
Positive Pulse Duty Cycle
Rise or Fall Time
High Level Voltage
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Pull-Down Resistor
POWER GOOD
Internal Power-Good
Rising Threshold
Hysteresis
Falling Delay
Rising Delay for PWRGD Pin
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
INTERNAL REGULATORS
VDD
Output Voltage
Current Limit
VREG
Output Voltage
Dropout Voltage
Current Limit
THERMAL SHUTDOWN
Threshold
Hysteresis
Symbol
VIN
IQ
ISHDN
UVLO
VUVLO-RISING
VUVLO-FALLING
VHYS
fSW
fSYNC
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
fCLK
tCLK_PULSE_DUTY
tCLK_RISE_FALL
VH (SYNC_OUT)
VTH_H (EN)
VTH _ L (EN )
RPULL-DOWN (EN)
Min Typ Max Unit Test Conditions/Comments
4.5
15.0 V
PVIN1, PVIN2, PVIN3, PVIN4 pins
PVIN1, PVIN2, PVIN3, PVIN4 pins
4.8 6.35 mA No switching, all ENx pins high
25 65 µA All ENx pins low
PVIN1, PVIN2, PVIN3, PVIN4 pins
4.2 4.36 V
3.6 3.78
V
0.42 V
700 740 780 kHz RT = 25.5 kΩ
250 1400 kHz
250 1400 kHz
100 ns
100 ns
1.3 V
0.4 V
fSW
50
10
VVREG
kHz
%
ns
V
0.688
0.806
0.725
1.0
0.832
V
V
MΩ
EN1, EN2, EN3, EN4 pins
VPWRGD (RISE)
VPWRGD (HYS)
tPWRGD_FALL
tPWRGD_PIN_RISE
IPWRGD_LEAKAGE
VPWRGD_LOW
86.3 90.5 95
%
3.3 %
50 µs
1 ms
0.1 1
µA
50 100 mV IPWRGD = 1 mA
VVDD
ILIM_VDD
VVREG
VDROPOUT
ILIM_VREG
TSHDN
THYS
3.2 3.305 3.4 V
IVDD = 10 mA
20 51 80 mA
4.9 5.1 5.3 V
225 mV IVREG = 50 mA
50 95 140 mA
150 °C
15 °C
Rev. B | Page 4 of 36
5 Page 
ADP5053
Data Sheet
Pin No.
32
33, 34
35, 36
37
38
39
40
41
42
43
44
45
46
47
48
0
Mnemonic
BST1
SW1
PVIN1
EN1
SS12
COMP1
FB1
RT
VDD
SYNC/MODE
VREG
FB3
COMP3
SS34
EN3
EPAD
Description
High-Side FET Driver Power Supply for Channel 1.
Switching Node Output for Channel 1.
Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass
capacitor between this pin and ground.
Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold.
Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and
Channel 2 (see the Soft Start section).This pin is also used to configure parallel operation of Channel 1 and Channel 2
(see the Parallel Operation section).
Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.
Feedback Sensing Input for Channel 1.
Frequency Setting. Connect a resistor from RT to ground to program the switching frequency from 250 kHz to
1.4 MHz. For more information, see the Oscillator section.
Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.
Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external
clock, connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. The SYNC function of
this pin can also be configured as a synchronization output by factory fuse.
Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, the device operates in
forced PWM (FPWM) mode. When this pin is logic low, the device operates in automatic PWM/PSM mode.
Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.
Feedback Sensing Input for Channel 3.
Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.
Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and
Channel 4 (see the Soft Start section).
Enable Input for Channel 3. Use an external resistor divider to set the turn-on threshold.
Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane.
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5053.PDF ] | |
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