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PDF ADP3654 Data sheet ( Hoja de datos )
| Número de pieza | ADP3654 | |
| Descripción | 4A MOSFET Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Speed, Dual,
4 A MOSFET Driver
ADP3654
FEATURES
GENERAL DESCRIPTION
Industry-standard-compatible pinout
High current drive capability
Precise UVLO comparator with hysteresis
3.3 V-compatible inputs
10 ns typical rise time and fall time at 2.2 nF load
Matched propagation delays between channels
Fast propagation delay
4.5 V to 18 V supply voltage
Parallelable dual outputs
Rated from −40°C to +125°C junction temperature
Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead
MINI_SO_EP
APPLICATIONS
AC-to-dc switch mode power supplies
DC-to-dc power supplies
Synchronous rectification
Motor drives
The ADP3654 high current and dual high speed driver is capable
of driving two independent N-channel power MOSFETs. The
driver uses the industry-standard footprint but adds high speed
switching performance.
The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
Digital power controllers are powered from a low voltage
supply, and the driver is powered from a higher voltage supply.
The ADP3654 driver adds UVLO and hysteresis functions,
allowing safe startup and shutdown of the higher voltage supply
when used with low voltage digital controllers.
The driver is available in thermally enhanced SOIC_N_EP and
MINI_SO_EP packaging to maximize high frequency and
current switching in a small printed circuit board (PCB) area.
FUNCTIONAL BLOCK DIAGRAM
NC 1
ADP3654
VDD
8 NC
INA 2
7 OUTA
PGND 3
INB 4
UVLO
6 VDD
5 OUTB
Figure 1.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP3654
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD
OUTA, OUTB
DC
<200 ns
INA, INB
ESD
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
SOIC_N_EP
MINI_SO_EP
θJA, JEDEC 4-Layer Board
SOIC_N_EP1
MINI_SO_EP1
Junction Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +20 V
−0.3 V to VDD + 0.3 V
−2 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
3.5 kV
1.5 kV
1.0 kV
59°C/W
43°C/W
−40°C to +150°C
−65°C to +150°C
300°C
215°C
260°C
1 θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as
appropriate with the exposed pad soldered to the PCB.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 4 of 13
5 Page 
ADP3654
Figure 16 shows an example of the typical layout based on the
preceding guidelines.
Figure 16. External Component Placement Example
Note that the exposed pad of the package is not directly con-
nected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground
of the device.
PARALLEL OPERATION
The two driver channels present in the ADP3654 device can be
combined to operate in parallel to increase drive capability and
minimize power dissipation in the driver.
The connection scheme is shown in Figure 17. In this configura-
tion, INA and INB are connected together, and OUTA and
OUTB are connected together.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
1 NC
ADP3654
NC 8
INA
2
OUTA
A7
3 PGND
VDD 6
VDD
VDS
4 INB
B OUTB 5
Figure 17. Parallel Operation
Data Sheet
THERMAL CONSIDERATIONS
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.
Data on package thermal resistance is provided in Table 2 to
help the designer with this task.
There are several equally important aspects that must be
considered, such as the following:
• Gate charge of the power MOSFET being driven
• Bias voltage value used to power the driver
• Maximum switching frequency of operation
• Value of external gate resistance
• Maximum ambient (and PCB) temperature
• Type of package
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as CISS, it is not
useful to calculate power losses.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under QG.
This parameter varies from a few nanocoulombs (nC) to several
hundred nC, and is specified at a specific VGS value (10 V
or 4.5 V).
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:
PGATE = VGS × QG × fSW
where:
VGS is the bias voltage powering the driver (VDD).
QG is the total gate charge.
fSW is the maximum switching frequency.
The power dissipated for each gate (PGATE) still needs to be
multiplied by the number of drivers (in this case, 1 or 2) being
used in each package, and it represents the total power dissi-
pated in charging and discharging the gates of the power
MOSFETs.
Not all of this power is dissipated in the gate driver because part
of it is actually dissipated in the external gate resistor, RG. The
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.
Rev. A | Page 10 of 13
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADP3654.PDF ] | |
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