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PDF ADP5091 Data sheet ( Hoja de datos )
| Número de pieza | ADP5091 | |
| Descripción | Ultralow Power Energy Harvester PMUs | |
| Fabricantes | Analog Devices | |
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Data Sheet
Ultralow Power Energy Harvester PMUs
with MPPT and Charge Management
ADP5091/ADP5092
FEATURES
Boost regulator with maximum power point tracking (MPPT)
with dynamic sensing or no sensing mode
Hysteresis mode for best ultralight load efficiency
Operating quiescent current of SYS pin (VIN > VCBP ≥ VMINOP): 510 nA
Sleeping quiescent current of SYS pin (VCBP < VMINOP): 390 nA
Input voltage operating range: 0.08 V to 3.3 V
Fast cold start from 380 mV (typical) with charge pump
Programmable shutdown point on MINOP pin based on the
input open circuit voltage (OCV)
150 mA regulated output from 1.5 V to 3.6 V
Battery terminal charging threshold (2.2 V to 5.2 V) to
support charging storage elements
Optional BACK_UP power path management
Radio frequency (RF) transmission conducive to shutting
down the switcher temporarily via microcontroller unit
(MCU) communication
APPLICATIONS
Photovoltaic (PV) cell energy harvesting
Thermoelectric generators (TEGs) energy harvesting
Industrial monitoring
Self powered wireless sensor devices
Portable and wearable devices with energy harvesting
GENERAL DESCRIPTION
The ADP5091/ADP5092 are intelligent, integrated energy
harvesting, ultralow power management unit (PMU) solutions
that convert dc power from PV cells or TEGs. These devices charge
storage elements such as rechargeable Li-Ion batteries, thin film
batteries, super capacitors, or conventional capacitors, and
power up small electronic devices and battery free systems.
The ADP5091/ADP5092 provide efficient conversion of the
harvested limited power from a 6 µW to 600 mW range with
submicrowatt operation losses. With the internal cold start circuit,
the regulator can start operating at an input voltage as low as
380 mV. After cold startup, the regulator is functional at an
input voltage range of 0.08 V to 3.3 V. An additional 150 mA
regulated output can be programmed by an external resistor
divider or the VID pin.
The MPPT control keeps the input voltage ripple in a fixed range to
maintain stable dc-to-dc boost conversion. The dynamic sensing
mode and no sensing mode, both programming regulation points
of the input voltage, allow extraction of the highest possible energy
from the harvester. A programmable minimum operation
threshold enables boost shutdown during a low input condition.
TYPICAL APPLICATION CIRCUIT
FROM MCU
PIN
REG_D0
REG_D1
VID
SW
VIN
ADP5091
HYSTERESIS
REGULATOR
AND LDO
COLD START
CHARGE PUMP
LLD
REG_OUT
REG_FB
PGOOD
SYS
TO MCU
TO MCU
SYSTEM
LOAD
FROM MCU
OPTIONAL +
PRIMARY –
BATTERY
MPPT
CBP
MPPT
BOOST
CONTROL REGULATOR
BAT
REF
MINOP
CHARGE CONTROL
AND
POWER PATH
MANAGEMENT
SETSD
SETPG
DIS_SW
BACK_UP
AGND PGND
SETHYST
SETBK
TERM
+ RECHARGEABLE
–
BATTERY OR
SUPERCAP
Figure 1.
As a low light indicator for a microprocessor, the LLD pin of the
ADP5091 is the MINOP comparator output. However, the
REG_GOOD flag of the ADP5092 monitors the REG_OUT
voltage. In addition, the DIS_SW pin can temporarily shut down
the boost regulator and is RF transmission friendly.
The charging control function of the ADP5091/ADP5092 protects
the rechargeable energy storage, which is achieved by monitoring
the battery voltage with the programmable charging termination
voltage and the shutdown discharging voltage. In addition, a
programmable PGOOD flag monitors the SYS voltage.
An optional primary cell battery can be connected and managed
by an integrated power path management control block that is
programmable to switch the power source from the energy
harvester, rechargeable battery, and primary cell battery.
The ADP5091/ADP5092 are available in a 24-lead LFCSP and
are rated for a −40°C to +125°C temperature range.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
ENERGY STORAGE MANAGEMENT
Internal Reference Voltage
Battery Stop Discharging
Threshold
Hysteresis Resistor
Battery Terminal Charging
Threshold
Hysteresis
PGOOD Rising Threshold at SYS Pin
PGOOD Pull-Up Resistor
PGOOD Pull-Down Resistor
PGOOD High Voltage
Battery Switches On Resistance
Battery Source Current
Leakage Current at BAT Pin
BACK_UP POWER PATH
Turning Off BACK_UP Switch
Threshold on BAT
Hysteresis Resistor
BACK_UP Switches On Resistance
BACK_UP and BAT Comparator
Offset
Hysteresis
BACK_UP Current Capability
Leakage Current at BACK_UP Pin
THERMAL SHUTDOWN
Threshold
Hysteresis
Symbol Test Conditions/Comments
VINT_REF
VSETSD
RSETSD_HYS
VBAT_TERM
VBAT_TERM_HYS
VSYS_PG
VPGOOD_HIGH
RBAT_SW_ON
IBAT
IBAT_LEAK
Pin to pin measurement
VBAT = 2 V, VSETSD = 2.2 V, VSYS = 2 V
VBAT = 3.3 V, VSETSD = 2.2 V, VSYS = 0 V
VSETBK
RSETBK_HYS
VBKP_OFFSET
VBAT_HYS
IBKP
IBKP_LEAK
VSYS ≥ VSYS_TH
VSYS < VSYS_TH
VBACK_UP = VSYS = VBAT = 3 V
TSHDN
THYS
VSYS ≥ VSYS_TH
ADP5091/ADP5092
Min
0.955
2.0
80
2.2
VSETSD
Typ
1.011
115
3
11.6
11.6
VSYS
0.59
22
3.5
Max Unit
1.067 V
VBAT_TERM V
160 kΩ
5.2
3.1
VBAT_TERM
17.0
17.0
0.85
1
50
35
V
%
V
kΩ
kΩ
V
Ω
A
nA
nA
2.0 VBAT_TERM V
80 115 160 kΩ
0.85 1.20 Ω
158 190 271 mV
68 75 108 mV
250 µA
16 40 nA
142 °C
15 °C
Rev. 0 | Page 5 of 28
5 Page 
Data Sheet
100
95
90
85
80
75
70
65 SYS = 3V
SYS = 5V
60
0.01 0.1
1
10
INPUT CURRENT (mA)
Figure 11. Efficiency vs. Input Current, VIN = 2 V
100
100
90
80
70
60
50
40
30
20
10
0
.02
SYS = 3V
SYS = 5V
0.2 2
INPUT CURRENT (mA)
20
Figure 12. Efficiency vs. Input Current, VIN = 1 V, VREG_OUT = 2 V, IREG_OUT = 10 µA
1600
1400
1200
1000
800
600
400 TA = –40°C
TA = +25°C
200
TA = +85°C
TA = +125°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
SYS VOLTAGE (V)
Figure 13. Quiescent Current vs. SYS Voltage, VREG_D0 = VREG_D1 = VSYS, VMINOP ≤ VCBP
ADP5091/ADP5092
100
90
80
70
60
50
40
30
20
10
0
.05
SYS = 3V
SYS = 5V
0.5 5
INPUT CURRENT (mA)
50
Figure 14. Efficiency vs. Input Current, VIN = 0.5 V, VREG_OUT = 2 V,
IREG_OUT = 10 µA
1400
1200
1000
800
600
400
TA = –40°C
200
TA = +25°C
TA = +85°C
TA = +125°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
SYS VOLTAGE (V)
Figure 15. Quiescent Current vs. SYS Voltage, VMINOP ≤ VCBP
1200
1000
800
600
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
400
200
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
SYS VOLTAGE (V)
Figure 16. Quiescent Current vs. SYS Voltage, VMINOP > VCBP
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADP5091.PDF ] | |
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