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PDF AD5383 Data sheet ( Hoja de datos )
| Número de pieza | AD5383 | |
| Descripción | 12-Bit denseDAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
32-Channel, 3 V/5 V, Single-Supply,
12-Bit, denseDAC
AD5383
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I2C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical microelectro-mechanical systems (MEMS)
Control systems
Instrumentation
DVDD (×3)
DGND (×3)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×4)
AGND (×4) DAC GND (×4)
REFGND
REFOUT/REFIN SIGNAL GND (×4)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I2C)
DB8
DB0
A4
A0
REG 0
REG 1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
AD5383
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
VOUT0………VOUT31
36-TO-1
MUX
12 INPUT 12
REG 0
12 m REG 0
12 c REG 0
12 INPUT 12
REG 1
12 m REG 1
12 c REG 1
12 INPUT 12
REG 6
12 m REG 6
12 c REG 6
12 INPUT 12
REG 7
12 m REG 7
12 c REG 7
×4
1.25V/2.5V
REFERENCE
12
DAC 12
REG 0
DAC 0
12
DAC 12
REG 1
DAC 1
12
DAC 12
REG 6
DAC 6
12
DAC 12
REG 7
DAC 7
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT31
MON_OUT
Figure 1.
LDAC
Rev. D
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5383
GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit
denseDAC® available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference; an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring; and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
features
• Double-buffered parallel interface with a 20 ns WR
pulse width.
• SPI-/QSPI-/MICROWIRE-/DSP-compatible serial
interface with interface speeds in excess of 30 MHz.
• I2C-compatible interface that supports a 400 kHz data
transfer rate.
Data Sheet
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated independently
or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust register
that allows the user to fully calibrate any DAC channel. With
boost off, power consumption is typically 0.25 mA/channel.
Rev. D | Page 4 of 40
5 Page 
AD5383
SCLK
SYNC
DIN
SDO
SCLK
SYNC
DIN
SDO
LDAC
SCLK
SYNC
t4
t7
t3
t6
t8 t9
t1
24
t2 t5
24
DIN
BUSY
LDAC1
VOUT1
LDAC2
VOUT2
CLR
DB23
t18
DB0
t10
t11
t12 t13
t15
t17
t14
t13
t16 t17
t19
VOUT 1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
24
t7A
48
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
NOP CONDITION
DB0
UNDEFINED
SELECTED REGISTER
DATA CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
t1
t7
t4
24
t3 t2
48
t21
t22
t8 t9
DB23
DB0 DB23
DB0
INPUT WORD FOR DAC N
t20
INPUT WORD FOR DAC N+1
DB23
DB0
UNDEFINED
INPUT WORD FOR DAC N
t13
t23
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. D | Page 10 of 40
Data Sheet
11 Page | ||
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| PDF Descargar | [ Datasheet AD5383.PDF ] | |
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