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PDF AD5317R Data sheet ( Hoja de datos )
| Número de pieza | AD5317R | |
| Descripción | Quad 10-Bit nanoDAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Quad, 10-Bit nanoDAC®
with 2 ppm/°C Reference, SPI Interface
AD5317R
FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5317R, a member of the nanoDAC® family, is a low
power, quad, 10-bit buffered voltage output DAC. The device
includes a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The device operates from a single
2.7 V to 5.5 V supply, is guaranteed monotonic by design, and
exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.
The AD5317R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain at that level until a valid write
takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.
The AD5317R employs a versatile SPI interface that operates at
clock rates up to 50 MHz and contains a VLOGIC pin intended for
1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCLK
SYNC
SDIN
SDO
AD5317R
2.5V
REFERENCE
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
POWER-ON
RESET
GAIN
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
12-Bit
AD5684R
AD5684
AD5694R
AD5694
10-Bit
AD53171
AD5316R
AD5316
1 The AD5317 and AD5317R are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5317R
Data Sheet
Parameter
LOGIC INPUTS2
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode9
All Power-Down Modes10
Min
Typ Max
Unit
0.7 × VLOGIC
2
±2
0.3 × VLOGIC
µA
V
V
pF
VLOGIC − 0.4
4
0.4
V
V
pF
Test Conditions/Comments
Per pin
ISINK = 200 μA
ISOURCE = 200 μA
1.8
2.7
VREF + 1.5
5.5
3
5.5
5.5
0.59 0.7
1.1 1.3
14
6
V
µA
V Gain = 1
V Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
mA Internal reference off
mA Internal reference on, at full scale
µA −40°C to +85°C
µA −40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
2 Guaranteed by design and characterization; not production tested.
3 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 28).
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
10 All DACs powered down.
Rev. A | Page 4 of 28
5 Page 
AD5317R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5317R
Data Sheet
VOUTA 1
GND 2
VDD 3
VOUTC 4
12 SDIN
11 SYNC
10 SCLK
9 VLOGIC
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 6. 16-Lead LFCSP Pin Configuration
VREF 1
VOUTB 2
VOUTA 3
GND 4
VDD 5
VOUTC 6
VOUTD 7
SDO 8
16 RSTSEL
15 RESET
14 SDIN
AD5317R
TOP VIEW 13 SYNC
(Not to Scale) 12 SCLK
11 VLOGIC
10 GAIN
9 LDAC
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP TSSOP
Mnemonic
13
VOUTA
24
GND
35
VDD
46
57
68
VOUTC
VOUTD
SDO
79
LDAC
8 10
9 11
10 12
11 13
12 14
13 15
GAIN
VLOGIC
SCLK
SYNC
SDIN
RESET
14 16
15 1
16 2
17 N/A
RSTSEL
VREF
VOUTB
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. This part can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5317R devices together or can be
used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling
edge of the clock.
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to be simultaneously updated. This pin can also be tied permanently low.
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this
pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses
are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale
or midscale, depending on the state of the RSTSEL pin. If the pin is not used, tie it permanently to VLOGIC.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VLOGIC powers up all four DACs to midscale.
Reference Voltage. The AD5317R has a common reference pin. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference output.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD5317R.PDF ] | |
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