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PDF AD5697R Data sheet ( Hoja de datos )
| Número de pieza | AD5697R | |
| Descripción | Dual 12-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual, 12-Bit nanoDAC+
with 2 ppm/°C Reference, I2C Interface
AD5697R
FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of full-scale range (FSR)
maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Base station power amplifiers
Process controls (programmable logic controller [PLC] I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5697R, a member of the nanoDAC+™ family, is a low power,
dual, 12-bit buffered voltage output digital-to-analog converter
(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference
(enabled by default) and a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from
a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,
and exhibits less than 0.1% FSR gain error and 1.5 mV offset
error performance. The device is available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
The AD5697R also incorporates a power-on reset circuit and a
RSTSEL pin that ensure that the DAC outputs power up to zero
scale or midscale and remain there until a valid write takes
place. It contains a per channel power-down feature that reduces
the current consumption of the device to 4 µA at 3 V while in
power-down mode.
The AD5697R uses a versatile 2-wire serial interface that operates
at clock rates up to 400 kHz and includes a VLOGIC pin intended
for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
AD5697R
SDA
INPUT
REGISTER
A1 INPUT
REGISTER
A0
2.5V
REFERENCE
DAC
REGISTER
STRING
DAC A
DAC
STRING
REGISTER DAC B
BUFFER
BUFFER
VOUTA
VOUTB
LDAC RESET
POWER-ON
RESET
GAIN =
×1/×2
RSTSEL
GAIN
Figure 1.
POWER-
DOWN
LOGIC
Table 1. Dual nanoDAC+ Devices
Interface
Reference
16-Bit
SPI
Internal
AD5689R
External
AD5689
I2C Internal
12-Bit
AD5687R
AD5687
AD5697R
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5697R
Data Sheet
Parameter
Min Typ Max
LOGIC OUTPUTS (SDA)2
Output Low Voltage, VOL
0.4
Floating State Output Capacitance
4
POWER REQUIREMENTS
VLOGIC
1.62 5.5
ILOGIC
3
VDD 2.7 5.5
VREF + 1.5
5.5
IDD
Normal Mode9
0.59 0.7
1.1 1.3
All Power-Down Modes10
14
6
Unit Test Conditions/Comments
V ISINK = 3 mA
pF
V
µA
V Gain = 1
V Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
mA Internal reference off
mA Internal reference on, at full scale
µA −40°C to +85°C
µA −40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2 Guaranteed by design and characterization; not production tested.
3 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA up to a junction temperature of 100°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output device.
For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 25).
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. Both DACs active. DAC outputs unloaded.
10 Both DACs powered down.
Rev. B | Page 4 of 27
5 Page 
AD5697R
10
8
6
4
2
0
–2
–4
–6
–8
VDD = 5V
TA = 25°C
–10 INTERNAL REFERENCE = 2.5V
0 625 1250 1875
2500
3125
3750 4096
CODE
Figure 11. Integral Nonlinearity (INL) vs. Code
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
VDD = 5V
TA = 25°C
–1.0 INTERNAL REFERENCE = 2.5V
0 625 1250 1875
2500
CODE
3125
3750 4096
Figure 12. Differential Nonlinearity (DNL) vs. Code
10
8
6
4
2 INL
0
DNL
–2
–4
–6
–8 VDD = 5V
–10 INTERNAL REFERENCE = 2.5V
–40 10
60
TEMPERATURE (°C)
110
Figure 13. INL Error and DNL Error vs. Temperature
Data Sheet
10
8
6
4
2
INL
0
DNL
–2
–4
–6
–8 VDD = 5V
–10 TA = 25°C
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
Figure 14. INL Error and DNL Error vs. VREF
10
8
6
4
2
INL
0
DNL
–2
–4
–6
–8 TA = 25°C
–10 INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 15. INL Error and DNL Error vs. Supply Voltage
0.10
0.08
0.06
0.04
0.02
FULL-SCALE ERROR
0
–0.02
GAIN ERROR
–0.04
–0.06
–0.08 VDD = 5V
–0.10 INTERNAL REFERENCE = 2.5V
–40 –20 0
20 40
60
TEMPERATURE (°C)
80
100 120
Figure 16. Gain Error and Full-Scale Error vs. Temperature
Rev. B | Page 10 of 27
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5697R.PDF ] | |
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