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PDF AD5311R Data sheet ( Hoja de datos )
| Número de pieza | AD5311R | |
| Descripción | 10-Bit nanoDAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
10-Bit nanoDAC with SPI/I2C Interface
and 2 ppm/°C On-Chip Reference
AD5310R/AD5311R
FEATURES
High relative accuracy (INL): ±0.5 LSB maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
Independent logic supply: 1.8 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
Optical modules
GENERAL DESCRIPTION
The AD5310R/AD5311R, members of the nanoDAC® family, are
low power, single-channel, 10-bit buffered voltage output DACs.
The devices include an enabled by default internal 2.5 V
reference, and provides 2 ppm/°C. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in 10-lead
MSOP packages.
The internal power-on reset circuit of the AD5310R/AD5311R
ensures that the DAC register is written to zero scale at powerup
when the internal output buffer is configured in normal mode.
The devices contain a power-down mode that reduces the
current consumption of the device to 2 µA at 5 V.
The AD5310R/AD5311R use a versatile SPI or I2C interface,
including an asynchronous RESET pin and a VLOGIC pin that
provides 1.8 V compatibility.
LDAC
RESET
FUNCTIONAL BLOCK DIAGRAMS
VLOGIC
VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
10-BIT
DAC
AD5310R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK SDI
GND
Figure 1. AD5310R
VLOGIC
VREF
VDD
LDAC
RESET
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
10-BIT
DAC
AD5311R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SDA SCL
A0 GND
Figure 2. AD5311R
Table 1. Related Devices
Interface
Reference
SPI External
I2C External
12-Bit
AD5681R
10-Bit
AD53101
AD53111
1 The AD5310R and AD5311R are not pin-to-pin or software compatible with
the AD5310 and AD5311, respectively.
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL): ±0.5 LSB maximum.
2. Low Drift 2.5 V On-Chip Reference: 5 ppm/°C maximum
temperature coefficient.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5310R/AD5311R
TIMING CHARACTERISTICS
AD5310R
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Falling Edge to SCLK Fall Ignore
SYNC Rising Edge to SCLK Falling Edge
SYNC Rising Edge to LDAC Falling Edge
LDAC Pulse Width Low
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
SYNC Rising Edge to SYNC Rising Edge (DAC
Updates)
LDAC Falling Edge to SYNC Rising Edge
Reference Power-Up3
Exit Shutdown3
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
tREF_POWER_UP4
tSHUTDOWN 5
1.8 V ≤ VLOGIC ≤ 2.7 V
Min Typ Max
33
16
16
15
5
5
15
20
16
25
20
75
150
1.9
1.8
600
6
2.7 V ≤ VLOGIC2 ≤ 5.5 V
Min Typ Max
20
10
10
10
5
5
10
20
10
25
15
75
150
1.7
1.65
600
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin.
3 Not shown in Figure 3.
4 Same timing must be expected when powering up the device after VDD = 2.7 V.
5 Time required to exit power-down to normal mode of AD5310R/AD5311R operation; SYNC rising edge to 90% of DAC midscale value, with output unloaded.
Timing and Circuit Diagrams
SCLK
t4
t9
t2
t8 t3
SYNC
t1
SDI DB23 DB22 DB21 DB20
t7
t10
DB2
t5
t6
DB1
DB0
t15
LDAC
RESET
VOUT
t11
t12
t13
t14
Figure 3. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note)
t16
Rev. B | Page 5 of 24
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
200 400 600 800 1000
CODE
Figure 8. INL
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
200 400 600
CODE
Figure 9. TUE vs. Code
800
1000
0.04
TA = 25°C
GAIN = 1
0.03 VREF = 2.5V
0.02
0.01
U1 INTERNAL REFERENCE
0
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
–0.01
–0.02
2.70
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
3.30 3.75 4.25
4.75
VDD (V)
Figure 10. TUE vs. Supply, Gain = 1
5.25
AD5310R/AD5311R
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
200
0.06
0.04
0.02
U1_EXT
U2_EXT
U3_EXT
U1_INT
U2_INT
U3_INT
400 600
CODE
Figure 11. DNL
VDD = 5V
GAIN = 1
VREF = 2.5V
800 1000
0
–0.02
–0.04
–40
0 40
TEMPERATURE (°C)
Figure 12. TUE vs. Temperature
80
500
VDD = 5V
450
400
350
ZS INTERNAL REFERENCE, GAIN = 1
300 FS EXTERNAL REFERENCE, GAIN = 2
FS INTERNAL REFERENCE, GAIN = 2
250 ZS INTERNAL REFERENCE, GAIN = 2
FS INTERNAL REFERENCE, GAIN = 1
200 FS EXTERNAL REFERENCE, GAIN = 1
150
100
50
0
–40
–20
0 20 40 60
TEMPERATURE (°C)
80
Figure 13. Supply Current vs. Temperature
105
Rev. B | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5311R.PDF ] | |
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