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PDF HMC5805ALS6 Data sheet ( Hoja de datos )

Número de pieza HMC5805ALS6
Descripción GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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HMC5805ALS6
v01.1216
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
DC - 40 GHz
Typical Applications
The HMC5805ALS6 is ideal for:
• Test Instrumentation
• Microwave Radio & VSAT
• Military & Space
• Telecom Infrastructure
• Fiber Optics
Functional Diagram
Features
High P1dB Output Power: 24.5 dBm
High Psat Output Power: 27 dBm
Gain: 11.5 dB
Output IP3: 29 dBm
Supply Voltage: +10 V @ 175 mA
16 Lead Ceramic 6x6 mm SMT Package: 36 mm2
General Description
The HMC5805ALS6 is a GaAs pHEMT MMIC Dis-
tributed Power Amplifier which operates between DC
and 40 GHz. The amplifier provides 11.5 dB of gain,
29 dBm output IP3 and +24 dBm of output power at
1 dB gain compression while requiring 175 mA from
a +10 V supply. The HMC5805ALS6 is ideal for EW,
ECM, Radar and test equipment applications. The
HMC5805ALS6 amplifier I/Os are internally matched
to 50 Ohms and the 6x6 mm SMT package is well
suited for automated assembly techniques.
Electrical Specifications, TA = +25° C, Vdd = +10 V, Vgg2 = +3.5 V, Idd = 175 mA*
Parameter
Min. Typ. Max.
Frequency Range
DC - 5
Gain
9 12.5
Gain Flatness
±1.0
Gain Variation Over Temperature
0.01
Input Return Loss
17
Output Return Loss
18
Output Power for 1 dB Compression (P1dB)
19
25
Saturated Output Power (Psat)
27
Output Third Order Intercept (IP3)
34
Noise Figure
4.5
Supply Current
(Idd) (Vdd= 10V, Vgg1= -0.8V Typ.)
175
* Adjust Vgg1 between -2 to 0 V to achieve Idd = 175 mA typical.
Min.
9
18
Typ.
5 - 30
11.5
±0.75
0.02
11
13
24.5
27
29
4
175
Max.
Min.
Typ.
30 - 40
11.5
±0.75
0.025
11
9
23
26
26
7
175
Max.
Units
GHz
dB
dB
dB/ °C
dB
dB
dBm
dBm
dBm
dB
mA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc.,
1 responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D

1 page




HMC5805ALS6 pdf
HMC5805ALS6
v01.1216
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
DC - 40 GHz
Output IP3 vs. Supply Voltage
@ Pout=12 dBm / Tone
40
36
32
28
24
20
0
5 10 15 20 25 30 35 40
FREQUENCY (GHz)
+8V +10V +11V
Output IM3 @ Vdd=+10V
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10
Pout/TONE (dBm)
2 GHz
8 GHz
14 GHz
20 GHz
12 14 16
24 GHz
28 GHz
30 GHz
Reverse Isolation vs. Temperature
0
-10
-20
-30
-40
-50
-60
-70
-80
0 4 8 12 16 20 24 28 32 36 40 44
FREQUENCY (GHz)
+25C
+85C
-40C
Output IM3 @ Vdd=+8V
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10 12 14 16
Pout/TONE (dBm)
2GHz
8GHz
14GHz
20GHz
24GHz
28GHz
30GHz
Output IM3 @ Vdd=+11V
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10
Pout/TONE (dBm)
2 GHz
8 GHz
14 GHz
20 GHz
12 14
24 GHz
28 GHz
30 GHz
16
Power Compression @ 20GHz
28
230
24 220
20 210
16 200
12 190
8 180
4 170
0 160
0 2 4 6 8 10 12 14 16 18
INPUT POWER (dBm)
Pout
Gain
PAE
Idd
For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
4

5 Page





HMC5805ALS6 arduino
HMC5805ALS6
v01.1216
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
DC - 40 GHz
Theory of Operation
The HMC5805ALS6 is a GaAs, pHEMT, MMIC power amplifier. Its basic architecture is that of a cascode distributed
amplifier which allows for control of DC bias for a drain and two gates. The cascode distributed architecture uses a
fundamental cell consisting of a stack of two field effect transistors (FETs) with the source of the upper FET connected
to the drain of the lower FET. The fundamental cell is then duplicated several times, with a transmission line feed-
ing the RFIN signal to the gates of the lower FETs and a separate transmission line interconnecting the drains of the
upper FETs and routing the amplified signal to the RFOUT/VDD pin. Additional circuit design techniques are used
around each cell to optimize the overall performance for broadband operation. The major benefit of this architecture
is that high performance is maintained across a bandwidth far greater than what a single instance of the fundamen-
tal cell would provide. Additionally, ACG1-ACG4 provide access to internal nodes which, when provided with the
recommended AC terminations to ground, ensure that the overall response remains flat across the widest possible
frequency range. A simplified Schematic of Architecture is shown in below.
Schematic of Architecture
ACG2
ACG1
T-Line
RFOUT/VDD
VGG2
RFIN T-Line
VGG1
ACG4 ACG3
For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
10

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