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PDF HMC742HFLP5E Data sheet ( Hoja de datos )
| Número de pieza | HMC742HFLP5E | |
| Descripción | 0.5dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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HMC742HFLP5E
v00.0211t
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL
Designer’s Kit
Available
VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz
Typical Applications
The HMC742HFLP5E is ideal for:
• Cellular/3G Infrastructure
• WiBro / WiMAX / 4G
• Microwave Radio & VSAT
• Test Equipment and Sensors
• IF & RF Applications
12
Functional Diagram
Features
-19 to 12.5 dB Gain Control in 0.5 dB Steps
Power-up State Selection
High Output IP3: +39 dBm
TTL/CMOS Compatible
Serial, Parallel, or latched Parallel Control
±0.25 dB Typical Gain Step Error
Single +5V Supply
32 Lead 5x5mm SMT Package: 25mm2
General Description
The HMC742HFLP5E is a digitally controlled variable
gain amplifier which operates from 0.5 GHz to 4
GHz, and can be programmed to provide from -19
dB attenuation, to 12.5 dB of gain, in 0.5 dB steps.
The HMC742HFLP5E delivers noise figure of 4 dB
in its maximum gain state, with output IP3 of up to
+39 dBm in any state. The dual mode gain control
interface accepts either a three-wire serial input or a 6
bit parallel word. The HMC742HFLP5E also features a
user selectable power up state and a serial output for
cascading other serially controlled Hittite components.
The HMC742HFLP5E is housed in an RoHS compliant
5x5 mm QFN leadless package, and requires minimal
external components.
12 - 1
Electrical Specifications, TA = +25° C, 50 Ohm System Vdd = +5V, Vs= +5V
Parameter
Min.
Typ.
Max.
Min.
Typ.
Frequency Range
500 - 2700
2700-4000
Gain (Maximum Gain State)
12.5
9
Gain Control Range
31.5
31.5
Input Return Loss
14 12
Output Return Loss
10 12
Gain Accuracy: (Referenced to Maximum Gain State)
All Gain States
± (0.3 + 4% of relative gain setting) Max
Output Power for 1 dB Compression
Output Third Order Intercept Point
(Two-Tone Output Power= 12 dBm Each Tone)
Noise Figure (Max Gain State)
Switching Characteristics tRISE, tFall (10 / 90% RF)
tON, tOFF (Latch Enable to 10 / 90% RF)
Supply Current (Amplifier)
Supply Current (Controller) Idd
130
21 22
39 38
4 4.5
30 30
60 60
150 175 130 150
0.12 0.25
0.12
Max.
175
0.25
Units
MHz
dB
dB
dB
dB
dB
dBm
dBm
dB
ns
ns
mA
mA
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1 page  
v00.0211
HMC742HFLP5E
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL
VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz
12
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. The DVGA
latches in the desired power-up state approximately
200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Absolute Maximum Ratings
RF Input Power at Max Gain [1]
17.5 dBm (T = +85 °C)
Digital Inputs (LE, SERIN, CLK, P/S,
DO-D5, PUP1, PUP2)
-0.5 to Vdd +0.5V
Controller Bias Voltage (Vdd)
5.6V
Amplifier Bias Voltage (Vcc)
5.5V
Channel Temperature
175 °C
Continuous Pdiss (T = 85 °C)
(derate 13.3 mW/°C above 85 °C) [2]
1.2 W
Thermal Resistance [3]
75.6 °C/W
Storage Temperature
-65 to +150 °C
Operating Temperature
-40 to +85 °C
ESD Sensitivity (HBM)
Class 1A
[1] The maximum RF input power increases by the same amount
the gain is reduced. The maximum input power at any state is no
more than 28 dBm.
[2] This value does not include the RF power dissipation in the
attenuator. The loss in the attenuator depends on the state of
the attenuator. The loss in the attenuator should be included to
determine the total power dissipation in the part.
[3] This value does not include the RF power dissipation in the
attenuator. The thermal resistance at different states of the
attenuator can be determined based on note [2]
Bias Voltage
Vdd (V)
+5.0
Vs (V)
+5.0
Idd (Typ.) (mA)
0.12
Is (mA)
150
PUP Truth Table
LE
PUP1
PUP2
Gain Relative to Maximum
Gain
000
-31.5
010
-24
001
-16
011
Insertion Loss
1XX
0 to -31.5 dB
Note: The logic state of D0 - D5 determines the
power-up state per truth table shown below when LE
is high at power-up.
Truth Table
Control Voltage Input
Gain
Relative to
D5 D4 D3 D2 D1 D0 Maximum
Gain
High High High High High High
0 dB
High High High High High Low
-0.5 dB
High High High High Low High
-1 dB
High High High Low High High
-2 dB
High High Low High High High
-4 dB
High Low High High High High
-8 dB
Low High High High High High
-16 dB
Low Low Low Low Low Low
-31.5 dB
Any combination of the above states will provide a reduction in
gain approximately equal to the sum of the bits selected.
Control Voltage Table
State
Low
High
Vdd = +3V
0 to 0.5V @ <1 µA
2 to 3V @ <1 µA
Vdd = +5V
0 to 0.8V @ <1 µA
2 to 5V @ <1 µA
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
12 - 5
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HMC742HFLP5E.PDF ] | |
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