CH7510 Datasheet PDF - Chrontel
| Part Number | CH7510 | |
| Description | DisplayPort Receiver | |
| Manufacturers | Chrontel | |
| Logo |  |
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There is a preview and CH7510 download ( pdf file ) link at the bottom of this page. Total 7 Pages | ||
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Chrontel
CH7510
Brief Datasheet
CH7510 DisplayPort Receiver with Integrated mini-LVDS Timing
Controller (TCON)
FEATURES
GENERAL DESCRIPTION
• Fully compliant with DisplayPort Specification version Chrontel’s CH7510 is a low-cost, low-power semi-
1.1a and Embedded DisplayPort (eDP) Specification conductor device that integrates a mini-LVDS timing
version 1.2.
controller (TCON). This device receives high-speed
• Support 2 Main Link Lanes at 1.62Gb/s or 2.7Gb/s link serialized video data and uses the Block Diagram, fully
rate programmable TCON to drive the LCD panel modules
• Support LCD panel with resolution up to 1920x1200 through integrated mini-LVDS interface, which is
@60Hz or 1366x768@120Hz.
operating in low-voltage and low EMI emission.
• Support 6 pairs and 8 pairs mini-LVDS output for both
6-bit and 8-bit LCD panel interface, with the maximum The CH7510 is designed to comply with DisplayPort
clock up to 300MHz
Specification 1.1a and Embedded DisplayPort
• Flexible TCON output control, and flexible mini-LVDS Specification version 1.2. It supports two Main Link lanes
output mapping
that are capable of receiving data rate running at 1.62Gb/s
• Support single clock mode: R/L mini-LVDS data output or 2.7Gb/s. The device can accept input data in 18-bit
with one common mini-LVDS clock.
6:6:6 or 24-bit 8:8:8 RGB digital formats.
• Support HDCP Amendment for Displayport Rev.1.1
• Support Gamma correction control
The high performance CH7510’s TCON consists of
• Support dithering and 6-bit + FRC
• Support Enhanced Framing Mode
programmable logic blocks for processing input video
• Support eDP Authentication: Alternative Scramble Seed data, configurable timing control signals and video data to
Reset and Alternative Framing
interface LCD Gate Drivers and Source Drivers. During
• 2 external clock configuration: 27MHz crystal, 27MHz system power up, setting the power on/off sequence for a
reference clock
particular LCD panel can be achieved through CH7510’s
• Support 2-level and 3-level Gate Drivers (output STV1 TCON configuration registers. This timing control
and STV2 at the same time), 8 programmable GPOs for information is stored in the BOOT ROM along with the
driving Source or Gate drivers in TFT LCD panel
• Programmable LCD panel power sequence
• Support internal test pattern
EDID information that will be used during the Link
Training through AUX Channel.
•
•
Blank panel during invalid input
Support OSD display when GPIO
pins
control
Back-
The
CH7510
has
a
luminance
control
function to
adjust
light Luminance
LCD backlight. The brightness control command sent
• Supports PWM. Backlight luminance level control through AUX Channel can be dynamically translated by
through AUX channel, and GPIO pin Support Dynamic CH7510 and converted into LCD backlight control signal.
Backlight Control (OSD display)
The CH7510 will save the last setting of brightness level
• Support analog current interface for light sensor
value in the BOOT ROMand use it upon power up.
• Support loading of CH9904 BOOT ROM when power
up Advanced Power Management Unit (PMU) is designed to
• Support updating BOOT ROM through I2C Slave or reduce power consumption in normal operation.
AUX CH
• Programmable power management. Support Hardware
fully power down control
• Spread spectrum control is available for transmitting
mini-LVDS signal
• Hot Plug Detection
• Achieve bit error rate <10-9 for raw transport data per
lane and symbol error rate <10-12 for control data
• Offered in a 68-pin QFN package
209-1000-024 Rev 0.3
2012-7-24
1
|
| |
 
CHRONTEL
63,64 In
RXP1, RXN1
68 In
RBIAS
3,4 Power
7,42 Power
8,45 Power
18,32 Power
21,35,40 Power
52 Power
60,66 Power
63 Power
67 Power
VDDPLL
DVDD
DGND
AVDD
AGND
VDDGPO
VDDRX
GNDRX
VDDBG
CH7510
Main link Lane 1 input
One pair of differential data input. It handles clock-embedded high speed
differential data input as DP standard
Band-gap bias
This pin should be left open or pulled low with a 10k resistor in the
application.
Stream PLL Power Supply (1.8V)
Digital Power Supply (1.8V)
Digital Power Ground
LVDS Power Supply (3.3V)
LVDS Power Ground
GPO Power Supply (3.3V)
Main link Power Supply (1.8V)
Main link Power Ground
Band-gap Power Supply (1.8V)
Note:
1.
2.
The Voltage of LVDD (3.3V) should be given earlier than the DVDD and AVDD. And after the
Powers are stable, please give a Resetb signal (low to high signal).
The rise slope time of DVDD(T4) should not be larger than 2ms.
209-1000-024 Rev 0.3
2012-7-24
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CH7510 electronic component. |
| Information | Total 7 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CH7510.PDF Datasheet ] | |
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