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PDF UPD8255 Data sheet ( Hoja de datos )
| Número de pieza | UPD8255 | |
| Descripción | PROGRAMMABLE PERIPHERAL INTERFACES | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD8255 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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NEe Microcomputers, Inc.
NE'C
fLPD8255
fLPD8255A·5
PROGRAMMABLE PERIPHERAL INTERFACES
D ESCR I PTI ON
The IlPD8255 and IlPD8255A-5 are general purpose programmable INPUT/OUTPUT
devices designed for use with the 8080A/8085A microprocessors. Twenty-four (24)
I/O lines may be programmed in two groups of twelve (group I and group II) and used
in three modes of operation. In the Basic mode, (MODE 0), each group of twelve I/O
pins may be programmed in sets of 4 to be iniJut or output. In the Strobed mode,
(MODE 1), each group may be programmed to have 8 lines of input or output. Three
of the remaining four pins in each group are used for handshaking strobes and interrupt
control signals. The Bidirectional Bus mode, (MODE 2), uses the 8 lines of Port A for
a bidirectional bus, and five lines from Port C for bus control signals. The IlPD8255
and IlPD8255A-5 are packaged in 40 pin plastic dual-in-line packages.
F EATU RES
• Fully Compatible with the 8080A/8085 Microprocessor Families
• All Inputs and Outputs TTL Compatible
• 24 Programmable I/O Pins
• Direct Bit SET/RESET Eases Control Application Interfaces
• 8 - 2 mA Darlington Drive Outputs for Printers and Displays (IlPD8255)
• 8 - 4 mA Darlington Drive Outputs for Printers and Displays (IlPD8255A-5)
• LSI Drastically Reduces System Package Count
• Standard 40 Pin Dual-In-Line Plastic and Ceramic Packages
PIN CONFIGURATION
PA3
PA2
PAl
PAo
RD
cs
GND
Al
AO
PC7
pC6
PC5
PC4
PCo
PCl
PC2
PC3
PBo
PBl
PB2
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10
I l PD
8255/
31
11 8255A-5 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
PA4
PA5
PA6
PA7
WR
RESET
Do
Dl
D2
D3
D4
D5
D6
D7
Vcc
PB7
PB6
PB5
PB4
PB3
PIN NAMES
D7- DO
RESET
es
RD
WR
AO. A,
PA7,PAO
PB7-PBO
pe7-pea
Vee
GND
Data Bus {SI-Dlrectlonal}
Reset Input
Chip Select
Read Input
Write Input
Port Address
Port A (Bit}
Port 8 (Bltl
Port C (Bit)
+5 Volts
o Volts
II
Rev/2
609
1 page  
TIMING WAVEFORMS
(CaNT.)
MODE 1
WR-----·,J
OBF ------+-+--+-......
INTR - - - - - - + -........dl
twiT
ACR-------+------~-~I
OUTPUT TO PERIPHERAL
fL PD825518255A·5
STB FROM PERIPHERAL
I B F - - - -_ _"'I
INTR---------4-~
__R5--------~-~~~I~ jf::::::t----
INPUT FROM
PER IPHERAL
MODE 2
WRITE
DATA FROM ~PD8080A TO ~PD8255 AND ~PD8255A
INTR
ACK FROM PERIPHERAL
STB FROM PERIPHERAL
IBF -------.....,
PERIPHERAL _ _ _ _ _ _ ~=;"';'==H_l
BUS
IRIB
R6------~-----~~--~
DATA FROM
PERIPHERAL TO ~PD8255
AND ~PD8255A-5
READ DATA FROM
~PD8255 AND ~FD8255A-5
TO ~PD8080A
CD WRNote:'
Any sequence where
occurs before ACK and STB occurs before Ri5. is permissible.
IINTR = IBF· MASK· STB· RD + OBF - MASK· ACK - WR)
o When the jJPD8255A~5 is set to Mode 1 or 2, OBF is reset 10 be high (logic 1).
613
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet UPD8255.PDF ] | |
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