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PDF UPD8251 Data sheet ( Hoja de datos )
| Número de pieza | UPD8251 | |
| Descripción | PROGRAMMABLE COMMUNICATIONS INTERFACE | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEe Microcomputers, Inc.
NEe
p.PD8251
p.PD8251A
PROGRAMMABLE COMMUNICATION INTERFACES
DESCRIPTION
The}.lPD8251 and}.lPD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters (USARTs) are designed for microcomputer systems data communications.
The USART is used as a peripheral and is programmed by the 8080A or other
processor to communicate in commonly used serial data transmission techniques includ·
ing IBM Bi-Sync. The USART receives serial data streams and converts them into
parallel data characters for the processor. While receiving serial data, the USART will
also accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors and control signals such as TxE and SYNDET, is available
to the processor at any time.
FEATURES
• Asynchronous or Synchronous Operation
Asynch ronous:
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (}.lPD8251 A)
Synchronous:
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
• Baud Rate (1X Mode) - DC to 56K Baud (}.lPD8251)
- DC to 64K Baud (}.lPD8251A)
• Full Duplex, Double Buffered Transmitter and Receiver
• Parity, Overrun and Framing Flags
• Fully Compatible with 8080A/8085/}.lPD780 (Z80TM)
• All Inputs and Outputs are TTL Compatible
• Single +5 Volt Supply, ±10%
• Separate Device Receive and Transmit TTL Clocks
• 28 Pin Plastic DIP Package
• N-Channel MOS Technology
PIN CONFIGURATION 02
RxROY
0,
00
vCC
~
Di'R
RTs
DSR
RESET
CLK
T.O
TxE
CTS"
SYNDET ("PD82511
SYNDET/BD ("PD8251A)
TxRDY
0,.00
CIO
RO
WR
CS
CLK
RESeT
TxC
TxO
RxC
RxO
RxRDY
TKRDY
Q.!lR
OTR
SYNDET
SVNDET/BO
RTS
CTS
T••
Vee
GNO
PIN NAMES
Data Bus 18 bitt)
Control or Data is to be Written or Read
And Data Command
Write Data or Control Command
Chip Enable
Clock Pulse (TTL!
R. ."
Transmitter Ctock (TTL)
Transmitter o.t.
Rewlve, Clock (TTL)
Receiver Data
Receiver Ready (has character for 8080)
Transmitter Readv (readv for char. from 80an
O.t. Set Rudy
Data Terminal Ready
Sync Oetect
Sync Detect/Break Detect
Requillt to Send Oat.
CI••r 10 Send Data
Transmitter Empty
+5 V04t Supply
Ground
II
TM: Z80 is a registered trademark of Zilog.
Rev/4
583
1 page  
TIMING WAVEFORM
,",PD825118251 A
CLOCK
SYSTEM CLOCK INPUT
~: ' " "ooEI
TPW -npo----j
~~
_
he (16x MODE)
T, DATA ~--I l--'oTX
r-'oTX ~t----------~x:::=
TRANSMITTER CLOCK AND DATA
Rx DATA
Axe (lx MODE)
Rxe (16 MODE)
INT SAMPLING
PULSE
(Rx BAUD COUNTER STARTS HERE)
ST ART BIT
- tRPW - - j -_ _ _ _ _-l\j
[}ATA BIT
RECEIVER CLOCK AND DATA
Tx RDY _ _--'I
DATA IN (0.6.1
c/o
DON'T CARE
DATA BIT
WRITE DATA CYCLE (PROCESSOR -+ USART)
Rx ROY
DATA OUT (D,B.) _ _ _~D~AT~A~F~L~O~A~T_ _-f~~~~~~~~~~
c/o
READ DATA CYCLE (PROCESSOR -+- USART)
II
587
5 Page 
,uPD8251/8251A
OPERATIONAL
DESCRIPTION
A set of control words must be sent to the IlPD8251 and IlPD8251 A to define the
desired mode and communications format. The control words will specify the BAUD
rate factor (1 x, 16x, 64x), character length (5 to 8), number of STOP bits (1, 1-1/2,
2) Asynchronous or Synchronous mode, SYNDET (IN or OUT), parity, etc.
After receiving the control words, the IlPD8251 and f-lPD8251A are ready to commun-
icate. TxRDY is raised to signal the processor that the USART is ready to receive a
character for transmission. When the processor writes a character to the USART,
TxR DY is automatically reset.
Concurrently, the IlPD8251 and IlPD8251A may receive serial data; and after
receiving an entire character, the RxRDY output is raised to indicate a completed
character is ready for the processor. The processor fetch will automatically reset
RxRDY.
Note:
The IlPD8251 and f-lPD8251A may provide faulty RxRDY for the first read
after power-on or for the first read after receive is re-enabled by a command
instruction (RxE). A dummy read is recommended to clear faulty RxRDY.
But this is not the case for the first read after hardware or software reset
after the device operation has once been established.
The IlPD8251 and f-lPD8251A cannot transmit until the TxEN (Transmitter
Enable) bit has been set by a Command Instruction and until the CTS (Clear
to Send) input is a "zero". TxD is held in the "marking" state after Reset
awaiting new control words.
uSA RT PROG RAM M ING
The USART must be loaded with a group of two to four control words provided by
the processor before data reception and transmission can begin. A RESET (internal or
external) must immediately proceed the control words which are used to program the
complete operational description of the communications interface. If an external
RESET is not available, three successive 00 Hex or two successive 80 Hex command
instructions (C/O ~ 1) followed by a software reset command instruction (40 Hex)
can be used to initialize the IlPD8251 and f-lPD8251A.
There are two control word formats:
1. Mode Instruction
2. Command Instruction
MODE INSTRUCTION
This control word specifies the general characteristics of the interface regarding the
Synchronous or Asynchronous mode, BAUD rate factor, character length, parity, and
number of stop bits. Once the Mode Instruction has been received, SYNC characters
or Command Instructions may be inserted depending on the Mode Instruction content.
COMMAND INSTRUCTION
This control word will be interpreted as a SYNC character definition if immediately
preceded by a Mode Instruction which specified a Synchronous format. After the
SYNC character(s) are specified or after an Asynchronous Mode Instruction, all sub-
sequent control words will be interpreted as an update to the Command Instruction.
Command Instruction updates may occur at any time during the data block. To
modify the Mode Instruction, a bit may be set in the Command Instruction which
causes an internal Reset which allows a new Mode Instruction to be accepted.
593
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet UPD8251.PDF ] | |
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