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Numéro de référence | UPD445L-1 | ||
Description | FULLY DECODED 4096 STATIC CMOS RAM | ||
Fabricant | NEC | ||
Logo | |||
NEe Microcomputers, Inc.
NEe
fLPD445L
fLPD445L·1
FULLY DECODED 4096 STATIC CMOS RAM
DESCRIPTION
The ~PD445L is a very low power 4,,096 bit (1024 words by 4 bits) static RAM fabricated
with NEC's complementary MOS (CMOS) process, It has two chip enable inputs (CE1,
CE2). Minimum standby current is drawn when CE1 is at a high level, while inhibiting
I I 'all address and control line transitions or, unconditionally when CE2 is at a low level.
This device ideally meets the low power requirements of battery operated systems and
battery back-up systems for non-volatility of data.
The ~PD445L uses fully static circuitry requiring no clocking. Output data is read out
non-destructively by placing a high on the R/W pin and has the same polarity as input
data. All inputs and outputs are directly TTL compatible. The device has common
input/output data busses and an OD (Output Disable) pin for use in common I/O bus
systems.
". The ~PD445L is guaranteed to retain data with the power supply voltage as low as 2.0
volts.
FEATURES
• Single +5V Power Supply
• Ideal for Battery Operation
• Low Standby Power fllr Dat,a Retention
• Simple Memory Expansion - Chip Enable Inputs
• Access Time - 650 ns Max. {J,tPD445L)
4.50 ns Max. (~PD445L-1)
• Directly TTL Compatible - All Inputs and Outputs
• Common Data Input and Output
• Static CMOS - No Clock or Refreshing Required
• 20 Pin Dual-In-Line Plastic Package
PIN CONFIGURATION
A3
A2
A,
AO
AS
As
A7
GNO
I/O,
1/°2
VCC
A4
R/W
eE,
00
CE2
A8
Ag
1/°4
1/03
PIN NAMES
Ao-Ag
00
R/W
CE,
CE2
1/0,-1/°4
VCC
GNO
Address Input
Output Disable
Read/Write.
Chip Enable'
Chip Enable 2
Data Input/Output
Power Supply
GrO\lnd
OPERATION MODES
CE, CE2 00
,0 0
, ,0
Others
Chip
Selected
Non-Selected
Output Mode
Data Out
High Impedance
93
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Pages | Pages 5 | ||
Télécharger | [ UPD445L-1 ] |
No | Description détaillée | Fabricant |
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