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PDF CDP1837C Data sheet ( Hoja de datos )
| Número de pieza | CDP1837C | |
| Descripción | 4096-Word x a-Bit Static Read-Only Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Read-Only Memories (ROMs)
CDP1837C
MA7
MAS
MA5
MA4
MA3
MA2
MAl
MAO
BUS 0
BUS I
BUS2
V5S
24
2 23
3 22
4 21
20
19
18
17
16
10 15
" 14
12 13
TOP VIEW
VDD
TPA
cn
CSI
CS2
MRD
CEO
BUS7
BUS6
BUS5
BUS4
BUS3
TERMINAL ASSIGNMENT
4096-Word X a-Bit Static
Read-Only Memory
Features:
• Interfaces with CDP1800-series microprocessors
(fCIOCk :s 5 MHz) without addItIonal components
• On-chip address latch
• On-chip address decoder provides programmable location within 64K
memory space
• Three-state outputs
The RCA-CDP1837C is a 32768-bit mask-programmable
CMOS read-only memory, organized as 4096 words x 8 bits
and is completely static: no clocks required. It will directly
interface with CDP1800-series microprocessors, having
clock frequencies up to 5 MHz, without additional
components.
The CDP1837C responds to a 16-bit address multiplexed on
8 address lines Address latches are provided on chip for
storing the high byte address data. By mask option, this
ROM can be programmed to operate in any 4096-word
block of 64-K memory space. The polarity of the high
address strobe (TPA), MRD, CEI, CS1, and CS2 are user
mask-programmable.
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be con~ected
in a daisy chain to control selection of RAM memory in a
microprocessor system without additional components.
The CDP1837C has a recommended operating voltage
range of 4 to 6.5 volts.
The CDP1837C is supplied in 24-lead heremetic dual-In-
Ime side-brazed ceramic packages (D suffix) and 24-lead
dual-in-line plastic packages (E suffix).
RAM
CPU
CDPIBOO
SERIES
IIO
Fig. 1 - Typical CDP1800 Sefles microprocessor system.
92Ct.l~35120
File Number 1381
_________________________________________________________________ 747
1 page  
Read-Only Memories (ROMs)
CDP1837C
JMA
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
TPA
(I )
MRD
f---'AS-
~ 1--, AH
-, PAW .....
, RSU \.00-
1\
tAVQV
(4)
tSVQV
-- t Rxel f----
-JI\
t AXQZ "I--
)
BUS
HIGH IMPEDANCE
(3 )
CEO
J--- t--'CEIO
---;
eEl:
'SVQX-
,D
OUTPUT
ACTIVE
LOW
!--'CA-
- t SXQZ ..t--
VALID DATA
f\---
Fig 4 - Timing diagram
92CM 37229
Notes:
(1) MRD must be valid on or before the trailing edge of
TPA. (Outp~ be tri-stated and the ROM powered
down when MRD is not valid.
(2) CS (CSl and CS2) controls the output buffers only.
Output will be tri-stated when either CSl or CS2 is not
valid.
(3) CEO is high when ROM is enabled.
(4) Provided tAVQV is satisfied.
_______________________________________________________________ 751
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| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CDP1837C.PDF ] | |
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