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PDF CDP1823 Data sheet ( Hoja de datos )
| Número de pieza | CDP1823 | |
| Descripción | 128-Word x 8-Bit Static Random-Access Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1823, CDP1823C
BLlS 0
eus I
2.
23
BUS 2
22
BUS 3
21
BuS 4
5
BUS 5- 6
20
19
BUS 6
8US 7
7
8
18
17
CSI 9 16
CS2
10
"c.53
V55 12
15
1" 3
TOP VIEW
VDD
MAO
MAl
MA2
MA3
MA'
MA5
MAS
MWR
-Mmi
ess
C54
TERMINAL ASSIGNMENT
128-Word X 8-Bit Static
Random-Access Memory
Features:
• Fast access time:
450 ns at Voo= 5 V;
250 ns at Voo = 10 V
• Common data inputs and outputs
• Multiple-chip select inputs to simplify
memory system expansion
The RCA-CDP1823 and CDP1823C are 128-word by 8-bit
CMOS SOS static random-access memories. These mem-
ories are compatible with general-purpose microprocessors.
The two memories are functionally identical. They differ in
that the CDP1823 has a recommended operating voltage
range of 4 to 10.5 volts, and the CDP1823C has a
recommended operating voltage range of 4 to 6.5 volts.
The CDP1823 memory has 8 common data input and data
output terminals for direct connection to a bidirectional
data bus and is operated from a single voltage supply. Five
chip-select inputs are provided to simplify memory-system
expansion. In order to enable the CDP1823, the chip-select
inputs CS2, ~, and CS5 require a low input signal, and
the chip-select inputs CS1 and CS4 require a high input
signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
Aftervalid data appear althe output, the address inputs may
be changed immediately. Output data will be valid until
either theMtm signal goes high, the device is deselected, or
tM (access time) after address changes.
The CDP1823 and CDP1823C are supplied in hermetic 24-
lead dual-in-line ceramic packages (D suffix), and in 24-
lead dual-in-line plastic packages (E suffix).
OPERATIONAL MODES
Function
READ
WRITE
STAND-BY (ACTIVE)
NOT
SELECTED
MAD MWR CS1 CS2 CS3 CS4 CS5 Bus Terminal State
Storage State of
0 X 1 0 0 1 0 Addressed Word
1 0 1 0 0 1 0 Input High-Impedance
1 1 1 0 0 1 0 High-Impedance
XX0 XXXX
XXX 1 XXX
X X X X 1 X X High-Impedance
XXXXX0 X
XXXXXX 1
Logic 1 = High Legic 0 = Low X = Don't Care
File Number 1198
660 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
1 page  
Random-Access Memories (RAMs) __________________________
CDP1823, CDP1823C
DATA RETENTION CHARACTERISTICS at TA = -40 to +85°C; see Fig. 3
CHARACTERISTIC
TEST
CONOI-
TIONS
VOR Voo
(V) (V)
LIMITS
COP1823
COP1823C
UNITS
Min. Typ." Max. Min. Typ." Max.
Min. Data Retention
--
- 1.5 2 - 1.5 2
V
Voltage,
VOR
Data Retention Quiescent 2 - - 30 100 - 30 100 J.lA
Current,
100
Chip Deselect to Data
-
5 600 -
- 600 -
-
Retention Time, tCOR
-
10 300 - - - - -
ns
Recovery to Normal
Operation Time, tRC
-
-
5 600 -
10 300 -
- 600 -
-- -
-
-
Voo to VOR Rise and
2
5 1- -
1-
-
J.ls
Fall Time
t"t,
"Typical values are for TA = 25° C and nominal Voo.
r =1CATA MROEDTEENTION
11V=OO---i.095 voo
095VOO.!t:----
feDR
cs,
rff
VOR f, - - ,
fRe
!fViH'ViH\ I ___1rVIL~___________
V,L
92CS-30805Rt
Fig. 3 - Low Voo data retentIOn timing waveforms.
MAO
MAl
MA2
MA3
BUFFER
ANO
DECODER
MA4
MA5-
MA6
CS'
CS2
CS3
CS4
Cs"'5
Functional Diagram
Fig. 4 - Functional diagram.
664 _______________________________________________
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CDP1823.PDF ] | |
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