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PDF CDM6264 Data sheet ( Hoja de datos )
| Número de pieza | CDM6264 | |
| Descripción | CMOS 8192-Word by 8-Bit LSI Static RAM | |
| Fabricantes | GE | |
| Logotipo |  |
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Random-Access Memories (RAMs) _______________________
CDM6264
NC
AI2
A7
A.
AS
••
A'
A2
AI
AD
1/01
1/02
I103
v••
••
6
10
.."12
I.
28 VDD
27 iVf
2. CE2
. .,2. A8
2.
.11
.'022 OE
21
m20
19 I/08
I. 1/07
17 I./08
I. 1/05
I. 1/04
TOP VIEW 91tS- 31209
TERMINAL ASSIGNMENT
CMOS 8192-Word by 8-Bit
LSI Static RAM
Features:
• Fully static operation
• Single power supply: 4.5 V to 5.5 V
• All inputs and outputs directly TTL
compatible
• Industry standard 2B-pin configuration
• Input address buffers gated off
with chip disable
• 3-state outputs
The RCA-CDM6264 is a 8192-word by B-bit static random-
access memory. It is designed for use in memory systems
where high-speed. low power and simplicity in use are
desirable. This device has common data input and data
output and utilizes a single power supply of 4.5 V to 5.5 V.
Either chip enable (00 or CE2). when not valid. will gate off
the address and output buffers and power down the chip to
minimum standby power with inputs toggling. The output
enable (OE) controls the. output buffers to eliminate bus
contention.
The CDM6264 is supplied in a 28-lead dual-in-line plastic (E
suffix) package.
AI2
All
A,AID
A. INPUT
ADDRESS
XV
DECODE
aUFFERS
A7
A'
..A.
A'
A'
AI
AO ENABLE
256. US
MEMORY
MATRIX
INPUTI
OUTPUT
DATA
BUFFERS
1/0'8
1/07
1/06
1/05
I104
1/03
1./02
:t/01
CiT
......-.-0 "'DO
CE' c~~~~gL 1-_ _ _ _ _ _ _ _ _ _ _ _--' 4-----0 Vss
Wi
9ZCIII-57210
0[
Fig. 1 - Functional block diagram.
CDM6284-3 FDM6264-21
Access Time (max)
150 ns
200 ns
Output Enable Time
(max.)
70 ns
70 n.
Operating Current
(max.)
45mA
45mA
Standby Current
100., (max.)
100pA 200pA
Operating Temp.
O·C to -40·C to
Range:
+70·C
+85·C
Data Retention Voltage:
O°CST",S+70°C
O°C::S; TA S +85°C
-40°CST",<0°C
2V min
-
-
-
2Vmin
4Vmin.
TRUTH TABLE
CE1 CE2 OE WE
H
X
L
L
-L
L - LOW
XX X
LXX
HLH
HXL
HH H
H - HIGH X - H OR L
AOTOA12
X
X
STABLE
STABLE
STABLE
MODE
NOT SELECTED
NOT SELECTED
READ
WRITE
OUTPUT DISABLE
DATA 110
HIGHZ
HIGHZ
DATA OUT
DATA IN
HIGHZ
DEVICE
CURRENT
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
File Number 1505
M2 ____________________________________________________________
1 page  
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDM6264
WRITE CYCLE 2 (CE2 CONTROL)
ADDRESS
rn
j 4 - - - - - IWC---------tIO'!
J------- 'AW
cn
DATA OUT~~~~~~~t_------------------------_+----------~~t_~
r'DW
'DH--1
DATA IN ------------~~~P---------~~~
IN A CI1 OR eE2 CONTROLLED WAITE CYCLE, THE-2,UTPUT BUFFERS
REMAIN IN A HIOH IMPEDANCE STATE, WHETHER OE IS HIOH OR LOW.
TIMING MEASUREMENT REFERENCE LEVEL IS 1.5 V.
':CM-37206
WRITE CYCLE 3 (WE CONTROL)
ADDRESS
j4------'WC---------~
CE2
DATA OUT
~'DW
'DH~
DATA IN --------~~~-------~~---
IFl!r IS HIGH DURING A WE CONTROLLED WRITE CYCLE,
THE OUTPUT BUFFERS REMAIN IN A HIGH IMPEDANCE STATE IN THIS PERIOD.
TIMING MEASUREMENT REFERENCE LEVEL IS 1.5 V
92CS-37207
Fig. 3 - Write-cycle timing waveforms (cont'd).
848 _______________________________________________________________
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CDM6264.PDF ] | |
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