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PDF CDP65C51 Data sheet ( Hoja de datos )
| Número de pieza | CDP65C51 | |
| Descripción | CMOS Asynchronous Communications Interface Adapter | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
Advance Information
TERMINAL ASSIGNMENT
vss
CSO
C51
RES
Rx C
XTLI
XTL
RTS
CTS
TxD
DTR
RxO
RSO
RS I
28
27
26
• 25
2.
23
7 22
8 21
20
10 I.
" 18
12 17
13 16
I. 15
TOP VIEW
R/W
~2
!l!1l
07
D6
D5
0"
03
02
01
DO
=
DCD
VDD
92CS-36774
CDP65C51
CMOS Asynchronous Communications
Interface Adapter (ACIA)
Features:
• Compatible with 8-blt microprocessors
• Full duplex operation with buffered
receiver and transmitter
• Data set/modem control functions
• Internal baud-rate generator with 15
programmable baud rates (50 to 19,200)
• Program-selectable internally or externally
controlled receiver rate
The RCA-CDP65C51 Asynchronous Communications Inter-
face Adapter (ACIA) provides an easily implemented,
program-controlled interface between 8-bit micropro-
cessor-based systems and serial communication data sets
and modems.
The CDP65C51 has an internal baud-rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, or 1/16 times an external clock rate. The Receiver
baud rate may be selected under program control to be
either the Transmitter rate, or at 1/16 times an external
clock rate The CDP65C51 has programmable word lengths
of 5,6,7, or 8 bits; even, odd, or no panty; 1, 1V2, or 2 stop
bits
The CDP65C51 is designed for maximum programmed
control from the CPU, to simplify hardware implementation.
Three separate registers permit the CPU to easily select the
CDP65C51 operating modes and data-checking parameters
and determine operational status.
The Command Register controls parity, receiver echo
mode, transmitter interrupt control, the state of the RTS
line, receiver interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
• Operates at baud rates up to 250,000 via
proper crystal or clock selection
• Programmable word lengths, number of stop
bits, and parity-bit generation and detection
• Programmable interrupt control
• Program reset
• Program-selectable serial echo mode
• Two chip selects
• 4-MHz, 2 MHz or 1 MHz operation (CDP65C51-4,
CDP65C51-2, CDP65C51-1, respectively)
• Single 3 V to 6 V power supply
• Full TTL compatibility
The Status Register indicates the states of the IRQ, DSR,
and DCD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing, and Panty Error conditions.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the CDP65C51 Transmit and
Receive circuits.
The CDP65C51-1, CDP65C51-2, and CDP65C51-4 are
capable of interfaCing with microprocessors with cycle
times of 1 MHz, 2 MHz and 4 MHz, respectively.
The CDP65C51 IS supplied in 28-lead, hermetic, dual-in-line
side brazed ceramic packages (D suffix), in 28-lead, dual-in-
line plastiC packages (E suffix) and in 28-lead dual-ln-Iine
small-outline (SO) packages (M) suffix.
File Number 1470
______________________________________________________________ 487
1 page  
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP65C51
CDP65C51 INTERNAL ORGANIZATION (Cont'd)
TIMING AND CONTROL
The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer, and the microprocessor data bus, and the
hardware reset features.
Timing is controlled by the system q,2 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the q,2 high period when selected.
All registers will be initialized by the Timing and Control
Logic when the Reset (RES) line goes low. Seethe individual
register description forthe state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used as temporary data storage for the
CDP65C51 Transmit and Receive circuits. Both the Trans-
mitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
Read/Write line determines which actually uses the internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (.Ieast significant bit first). The higher order
bits follow in order. Unused bits in this register are "don't
care".
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity
checking.
STATUS REGISTER
Fig.3 indicates the format of the CDP65C51 Status Register.
A description of each status bit follows.
76543210
IIIIIII"
L PARITY ERROR"
0- NO PARITY ERROR
1 - PARITY ERROR DETECTED
FRAMING ERROR·
a - NO FRAMING ERROR
1 - FRAMING ERROR DETECTED
" - - - OVERRUN'
a - NO OVERRUN
1 - OVERRUN HAS OCCURRED
RECEIVER DATA REGISTER FULL
a - NOT FULL
1 - FULL
TRANSMITTER DATA REGISTER EMPTY
a - NOT EMPTY
1 - EMPTY
DATA CARRIER DETECT (0C0)
0- 5C6 lOW (DETECn
1 - iSCij HIGH (NOT DETECTED)
DATA SET REAOY (DSR)
~= g~= ~~~(~NE~~~EADy)
INTERRUPT (IRQ)
O· NO INTERRUPT (IAQ PIN HIGH)
1 • INTERRUPT HAS OCCURRED (iJrn PIN LOW)
"NO INTERRUPTS OCCUR FOR
76543210
THESE CONDITIONS
11-1-1'1 I I°1 Ia a0 0 HAROWARE RESET (RES)
,- ,-, - ,-,- ,0 ,- ,-, PROGRAM RESET
92CM-367B3F11
Fig. 3 - Status register format.
Receiver Data Register Full (Bit 3)
This bit goes to a "1" when the CDP65C51 transfers data
from the Receiver Shift Register to the Receiver Data
Register, and goes to a "0" when the processor reads the
Receiver Data Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a "1" when the CDP65C51 transfers data
from the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and
Data Set Ready (Bit 6)
These bits reflect the levels of the DCD and DSR inputs to
the CDP65C51. A "0" indicates a low level (true condition)
and a "1" indicates a high (false). Whenever either of these
inputs changes state, an immediate processor interrupt
occurs, unless the CDP65C51 is disabled (bit 0 of the
Command Register is a "0"). When the interrupt occurs, the
status bits will indicate the levels of the inputs immediately
after the change of state occurred. Subsequent level changes
will not affect the status bits until the Status Register is
interrogated by the processor. At that time, another interrupt
will immediately occur and the status bits will reflect the
new input levels.
Framing Error (Bit 1), Overrun (Bit 2), and
Parity Error (Bit 0)
None of these bits causes a processor interrupt to occur,
but they are normally checked atthe time the Receiver Data
Register is read so that the validity of the data can be
verified.
Interrupt (Bit 7)
This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1" whenever any kind
of interrupt occurs.
CONTROL REGISTER
The Control Register selects the desired transmitter baud
rate, receiver clock source, word length, and the n umber of
stop bits.
Selected Baud Rate (Bits 0, 1, 2, 3)
These bits, set by the processor, select the Transmitter
baud rate, which can be at 1/16 an external clock rate or one
of 15 other rates controlled by the internal baud-rate
generator as shown in Fig. 4.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A "0"
causes the Receiver to operate at a baud rate of 1/16 an
external clock. A "1" causes the Receiver to operate at the
same baud rate as is selected forthetransmitter as shown in
Fig.4.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5,6,7 orB
bits). Fig. 4 shows the configuration for each numberof bits
desired.
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A "0"
always indicates one stop bit. A "1" indicates 1'12 stop bits if
the word length is 5 with no parity selected, 1 stop bit if the
word length is B with parity selected, and 2 stop bits in all
other configurations.
_______________________________________________________________ 491
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
CDP65C51
Effect of DCD on Receiver (Fig. 16)
CDP65C51 OPERATION (Cont'd)
DCD is a modem output used to indicate the status of the Once such a change of state occurs, subsequent transitions
carrter-frequency-detection circuit of the modem. This line will not cause interrupts or changes in the Status Register
goes high for a loss of carrier. Normally, when this occurs, until the first interrupt is serviced. When the Status Register
the modem will stop transmitting data (RxD on the is read by the processor, the CDP65C51 automatically
CDP65C51 some time later). The CDP65C51 will cause a checks the level of the DCD line, and if it has changed,
processor interrupt whenever DCD changes state and will another interrupt occurs.
indicate this condition via the Status Register.
I IBol B,I B211 G I rq;tI_GI:J LRXDBOGET~,J-:~:__J,S~T~D,P
r - - r_ _r-~-r------CD-N-T-'-NU-D-U-S-"-M-AR-K-"------~S~T~D,P
STOP
I ISTART
MODEM
I- MODEM -j
START
-~~1
I ~~ I
DCD __________________~----~Ir---~----------~I~--------_+--------------------+_--
II
IRQ
LIIrlJIll1'='-===::::;:1===::7JlJU
III
IL __.IltLlI
1~~6'~tE~LSOR
A~SF~LRO~N~GGEAHSR
1
PROCESSOR
I
NO INTERRUPT
WILL OCCUR
PROCESSOR
INTERRUPT
PROCESSOR
INTERRUPT
FOR DCI5
GOING HIGH
INTERRUPTS
FOR RECEIVER
WI LL OCCUR
INTERRUPT
FOR i5Co
GOING LOW
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
INTERRUPT
FOR
RECEIVER
DATA
DETECTED
Fig. 16 - Effect of DeD on receiver.
92CM-36786
Timing with 1'/' Stop Bits (Fig. 17)
It IS possible to select 1Y, Stop Bits, but this occurs only for processor interrupt for Receiver Data Register Full occurs
5-bit data words with no parity bit. In this case, the halfway through the trailing half-Stop Bit.
CHAR#n
I
CHAR#n+1
I
RxD
un L
f
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGH THE 1/2
STOP BIT
92CM- 36787
Fig. 17 - Timing with 1-112 stop bits.
Transmit Continuous "BREAK" (Fig. 18)
This mode is selected via the CDP65C51 Command Register
and causes the Transmitter to send continuous "BREAK"
characters after both the transmitter and transmitter-holding
registers have been emptied.
When the Command Register is programmed back to
normal transmit mode, a Stop Bit is generated and normal
transmission continues.
nSTOP
TxD
I ,STOP
GEI~bEJ
80 81 I
ISTART
START
BN P STOP
IRQ
/~------------~,/r-------
STOP
STOP
r~GG I ~
TART
rn------i
NORMAL
INTERRUPT
1 - - - - - - - - 1 -PERIOD DURING
WHICH PROCESSOR
SELECTS
CONTINUOUS
"BREAK" MODE
WHI~POINT AT
/
PROCESSOR
PROCESSOR
SEl.ECTS
INTERRUPT
NORMAL
TO LOAD
TRANSMIT
TRANSMIT
MODE
DATA
Fig. 18 - Transmit continuous "BREAK".
92CM-36785
_________________________________________________________________ 497
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CDP65C51.PDF ] | |
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