PDF CDP1874C Data sheet ( Hoja de datos )

Número de pieza	CDP1874C
Descripción	High-Speed 8-Bit Input and Output Ports
Fabricantes	GE
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No Preview Available ! _____________________________________ CMOS Peripherals CDP1872C, CDP1874C, CDP1875C (51 22 VDD 010 21 017 000 20 007 01 I 19 016 DO I 012 - 18 006 17 oro 002 16 005 Dt3 ~ 8 15 014 003 --- 14 004 CLOCK ~~~ 13 - CLR Vss ---~___ I.T- C52 TOP vIE W CDP1872C Input Port TERMINAL ASSIGNMENT High-Speed 8-Bit Input and Output Ports Features: • Parallel 8-bit input/output register with buffered outputs • High-spead data-in to data-out: 85 ns (max.) at Vee = 5 V • Flexible applications in microprocessor systems as buffers and latches • High order address-latch capability in CDP1800 series microprocessor systems • Output sink current = 5 mA (min.) at Vee = 5 V • 3-state output - CDP1872C and CDP1874C The RCA-COP1872C, COP1874C and COP1875C devices are high-speed 8-bit parallel input and output ports designed for use in the COP1800 microprocessor system and for general use in other microprocessor systems. The CDP1872C and COP1874C are 8-bit input ports; the COP1875C is an 8-bit output port. These devices have flexible capabilities as buffers and data latches and are reset by CLR input when the data strobe is not active. The CDP1872C and CDP1874C are functionally identical except for device selects. The CDP1872C has one active low and one active high select; the COP1874C has two active high device selects. These devices also feature 3- state outputs when deselected. Data is strobed into the register on the leading edge of the CLOCK and latched on the trailing edge of the CLOCK. The CDP1875C is an output port with data latched into the registers when the device selects are active. There are two active high and one active low selects. The output buffers are enabled at all ti meso .. These devices are supplied in 22-lead hermetic, dual-in-line side-brazed ceramic packages (0 suffix) and in 22-lead dual-in-line plastic package (E suffix). CSI 010 DOD 01 I 001 012 002 013 003 CLOCK VSS 22 21 20 4 19 5 18 17 16 15 14 10 13 " 12 TOP VIEW VDD 017 007 016 006 015 005 014 004 eLR CS2 92CS- 33011 CDP1874C Input Port TERMINAL ASSIGNMENT ,--~ CSi ~I 22 010 2 21 000 3 OIl ~4 001 5 20 19 18 012 --.-J6 17 002 17 16 DI3~15 003 9 14 C53 10 13 Yss II 12 - "'DO 017 007 016 006 015 005 014 004 CLR C52 TOP VIEW 92CS-33010 CDP1875C Output Port TERMINAL ASSIGNMENT File Number 1255 ________________________________________________ 425 1 page _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals CDP1872C, CDP1874C, CDP1875C I~ DO -07 '----- MRO NO- NI- N2- -DATA BUS I-- AO l-- AI I-- A2 Y, n- y,- - Y4- Y5- Ts- Y7- I - -CLOCK CS2 CDPl872C ~ DATA IN CSi CLOCK ~ ' - - CS2 CDPl802A CD74HC138 . - -DATA BUS ~ CSi ~CDPI872C DATA IN 92CS-33003R2 Fig. 7 - CDP1872C used as an input port and selected by CD74HC138. DATA IN ,--- CSI ~ Dr MRD CDPIB02 NO NI N2 00-07 I 1 CS2 DO CSI CS2 TPB- CS3 Dr DO CDPIB74C CDPIB75C DATA OUT III CSI CS2 CSI CS2 c=:)DATA IN DI DO Dr DO CDPI874C MEMORY TPB- CS3 CDPI875C 92C$-33002 Fig. 8-CDP1874C and CDP1875C used as mput/output buffers. DATA OUT ______________________________________________________________ 429 5 Page

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