CDP680SG2 Datasheet PDF - GE
| Part Number | CDP680SG2 | |
| Description | CMOS High-Performance Silicon-Gate 8-Bit Microcomputer | |
| Manufacturers | GE | |
| Logo |  |
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_________________ 680S-Series Microprocessors and Microcomputers
Product Preview
CDP680SG2, CDP680SG2C
TERMINAL ASSIGNMENT
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OSCI
om
TIMER
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TOP VIEW
CMOS High-Performance Silicon-Gate
a-Bit Microcomputer
Features:
• Typical full speed operating power
of 12 mWat5 V
• Typical WAIT mode power of 4 mW
• Typical STOP mode power of 5 /JW
• Fully static operation
• 112 bytes of on-chip RAM
• 2106 bytes 01 on-chip ROM
• 32 bidirectionalI/O lines
• High current drive'
• Internal B-bit timer with soltware
programmable 7-bit prescaler
• External timer input
• External and timer interrupts
• Self-check mode
• Master reset and power-on reset
• Single 3 to 6 volt supply
• On-chip oscillator with RC or crystal
mask options
• True bit manipulation
• Addressing modes with indexed
addressing for tables:
The CDP6805G2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer. The fully static design allows operation at frequencies
down to DC, further reducing its already low-power
consumption. It isa low-powerprocessordesigned for low-
end to mid-range applications in the consumer, automotive,
industrial, and communications markets where very low
power consumption constitutes an important factor.
-=-. .
TIMER
RESET NUM IRO
I3 2
Port
B
1/0
lines
PBO
PBI
PB2
PB3
PB4
PB5
PB6
PB7
Port
A
1/0
Lines
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
Port Data
B D"
Reg Reg
Port
A
Reg
Data
Dir
Reg
Accumulator
8A
Index
Register
8X
Condition
Code
Register CC
Stack
6 POinter
S
Program
Counter
High PCH
Program
Counter
8 low PCl
CPU
CPU
Control
AlU
Data
Dir
Reg
Port
C
Reg
Data
Dir
Reg
Port
D
Reg
PCO
PCI Pon
PC2 C
PC3 1/0
PC4 Lines
PC5
PC6
PC7
PDO
PDI
PD2
PD3
PD4
PD5
PD6
PD7
Port
D
1/0
Lines
198x8
Self· Check
ROM
Fig. 1 - CDP6805G2 CMOS microcomputer block diagram.
File Number 1364
------------___________________________________________________ 329
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP6805G2, CDP6805G2C
(;:SE(NS0ITI~VE~~:~*~~W////:0:I W&.:J~ffi
ONLY
~ t LCH
1920 teye
RESET
--------------------------------
~2* ------------------------~
.. INTERNAL TIMING SIGNALS NOT AVAILABLE EXTERNALLY,
* * REPRESENTS THE INTERNAL GATING OF THE CSCI INPUT PIN.
92CS-38101
Fig. 6 - Stop recovery and power-on RESET.
FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power IS supplied to the MCU uSing these two pins. VDD
IS power and VSS IS ground.
iRO (MASKABLE INTERRUPT REQUEST)
IRQ is mask option selectable With the choice of Interrupt
sensitivity being both level- and negative-edge or negatlve-
edge only.The MCU completes the current Instruction
before It responds to the request. If IRQ IS low and the Inter-
rupt mask bit II bit) In the condition code register IS clear, the
MCU beginS an Interrupt sequence at the end of the current
instruction.
If the mask option IS selected to Include level sensitivity,
then the IRQ Input requires an external resistor to VDD for
"wire-OR" operation. See the Interrupt section for more
detail
RESET
The RESET Input IS not required for start-up but can be
used to reset the MCU's Internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed deSCription
TIMER
The TIMER Input may be used as an external clock for the
on-chip lImer Refer to Timer section for a detailed deSCrip-
tion.
NUM - NON-USER MODE
This pin IS Intended for use In self-check only User ap-
plications should connect this pin to ground through a 10 kO
resistor
OSC1,OSC2
The CDP6805G2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived by either a divide-by-two or divide-
by-four of the external frequency (fOSC). Both of these
options are mask selectable.
RC - If the RC oscillator option IS selected, then a resistor
IS connected to the oscillator pms as shown In Figure 71b)
The relationship between Rand fosc IS shown In Figure 8.
CRYSTAL - The circuit shown In Figure 71a) IS recom-
mended when uSing a crystal. The Internal oscillator IS
deSigned to Interface With an AT-cut parallel resonant quartz
crystal resonator In the frequency range specified for fosc In
the electrical characteristics table. USing an external CMOS
oscillator IS suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the Input pins to minimize
output distortion and start-up stabilization time Crystal fre-
quency limits are also affected by VDD. Refer to Control
Timing Characteristics for limits. See Table 1
EXTERNAL CLOCK - An external clock should be ap-
plied to the OSC1 Input With the OSC2 Input not connected,
as shown In Figure 71e). An external clock may be used With
either the RC or crystal oscillator mask option. toxOV or
t)LCH do not apply when uSing an external clock input.
III
________________________________________________________________________________ 333
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CDP680SG2 electronic component. |
| Information | Total 22 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CDP680SG2.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| CDP680SG2 | The function is CMOS High-Performance Silicon-Gate 8-Bit Microcomputer. GE | |
| CDP680SG2C | The function is CMOS High-Performance Silicon-Gate 8-Bit Microcomputer. GE | |
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