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PDF CDP68HC05D2 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC05D2 | |
| Descripción | HCMOS Microcomputers | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05D2
HCMOS Microcomputer
Introduction
General
The CDP68HC05D2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer The fully static design allows operation at frequen-
cies down to DC, further reducing its already low-power
consumption. It is a low-power processor designed for low-
end to mid-range applications in the telecommunications,
consumer, automotive, and industrial markets where very
low power consumption constitutes an Important factor.
The CDP68HC05D2 is supplied in a 40-lead hermetic dual-
in-line side brazed ceramic package (0 suffix), a 40-lead
dual-in-line plastic package (E suffix), and a 44-lead Plastic
Chip Carner (Q suffix).
Specific Features
• Typical power:
Operating, 25 mW
WAIT,7.5mW
STOP,5p.W
Fully static operation
96 bytes of on-chip RAM
2176 bytes of on-chip ROM
31110 lines
12 programmable open-dram output lines
On-chip oscillator for Timer
2.1 MHz internal operating frequency
Internal 16-bit timer
Serial Peripheral Interface (SPI)
External (~), timer, Port B, and Serial Interrupts
Self check mode
Single 2.5 to 6 volt supply (2-V data retention mode)
RC or crystal on-chip OSCillator
8x8 multiply Instruction
True bit manipulation
Indexed addreSSing for tables
Memory mapped 110
Functional Pin Descriptions
Voo and Vss
Power is supplied to the MCU using these two pins Vee is
power and V•• is ground.
N.C.
The pin labelled N.C. should be left disconnected.
III
IRQ (Maskable Interrupt Request)
IRQ IS a programmable option which provides two different
chOices of interrupt triggering sensitivity. These options
are. 1) negative edge-sensitive triggering only, or 2) both
negative edge-sensitive and level-sensitive triggering. In
the latter case, either type of input to the IRQ pin will pro-
duce the interrupt. The MCU completes the current instruc-
tion before it responds to the interrupt request. When the
IRQ pin goes low for at least onet'LlH, a logic one is latched
internally to Signify that an interrupt has been requested.
When the MCU completes its current instruction, the inter-
rupt latch is tested. If the interrupt latch contains a logic
one, and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU then begins the interrupt se-
quence. If the option is selected to include level-sensitive
triggering, then the IRQ input requires an external resistor
to Vee for "wire-OR" operation. See the INTERRUPTS sec-
tion for more detail.
RESET
The RESET input IS not required for startup but can be used
to reset the MCU internal state and provide an orderly soft-
ware startup procedure. Refer to the RESETs section for a
detailed description
TSM-204A
________________________________________________________________________________ 193
1 page  
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05D2
DATA DIRECTION
REGISTER
BIT
INTERNAL
CDP68HC05D2
CONNECTIONS
LATCHED
OUTPUT DATA
BIT
110
PIN
TYPICAL PORT
DATA DIRECTION
REGISTER
TYPICAL PORT
REGISTER
PIN
92CS-39367
! 11111 ! 1
P-7 P-6 P-5 P-4 P-3 P-2 P-1 P-D
voo
"n"~ ••
PORT OOR
INTERN
LOGIC
AL
__-
<
l
<
I
-
-
-
-
-
-
J
NOTES:
1. -DENOTES DEVICES HAVE SAME
PHYSICAL SIZE, AND ARE
ENHANCEMENT TYPE.
=2. IP INPUT PROTECTION.
3. LATCH·UP PROTECTION NOT SHOWN.
92C5-42289
Fig. 3 - Typical Parallel Port I/O Circuitry
Table I - 110 Pin Functions
RtW* DDR
110 Pin Function
0 0 The I/O pin is in input mode. Data is written into the output data latch.
0 1 Data is written into the output data latch and output to the I/O pin.
1 0 The state of the I/O pin is read.
1 1 The 1/0 pin is in an output mode. The output data latch is read.
*RIW IS an Internal signal.
__________________________________________________________________ 197
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Series Microprocessors and Microcomputers
CDP68HC05D2
additional interrupts. The appropriate interrupt vector then
points to the starting address of the interrupt service routine
(refer to Fig. 4 for vector location). Upon completion of the
interrupt service routine, the RTI fnstruction (which IS nor-
mallya part of the service routine) causes the register con-
tents to be recovered from the stack followed by a return to
normal processing. The stack order is shown In Fig. 6.
Note: The Interrupt mask bit (I bit) will be cleared upon returning
from the interrupt if and only If the corresponding bit stored in the
stack IS zero The priority of the various interrupts is as follows
(highest Priority to lowest Priority'
RESET - ' - EXT INT - TIMER - SPI - Port B
'IS any instruction or the SWI service routine
A discussion of Interrupts, plus a table listing vector addresses for
all interrupts including reset, In the CDP68HC05D2 is provided in
Table V
Register
N/A
N/A
N/A
Timer Status
SPI Status
SpeCial
Port cis
Table V. Vector Address for Interrupts and Reset
Flag
Name
N/A
N/A
N/A
ICF
OCF
TOF
SPIF
MODF
Interrupts
Reset
Software
External Interrupt
Input Capture
Output Compare
Timer Overflow
Transfer Complete
Mode Fault
CPU
Interrupt
RESET
SWI
iRQ
TIMER
SPI
PBIF
Port B
PB
Vector
Address
$1 FFE-$1 FFF
$1 FFC-$1 FFD
$1 FFA-$1 FFB
$1 FFS-$1 FF9
$1 FF4-$1 FF5
$1 FF2-$1 FF3
Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT)
are not in the strictest sense an interrupt; however, they are
acted upon In a similar manner. Flowcharts for hardware
interrupts are shown in Fig. 9, and for STOP and WAIT are
provided in Fig. 10. A discussion is provided below:
• A low input on the RESET input pin causes the program to
vector to its starting address which is specified by the
contents of memory locations $1 FFE and $1 FFF. The I bit
in the condition code register is also set. Much of the
MCU is configured to a known state during this type of
reset as previously described in the RESET paragraph.
• STOP - The STOP instruction causes the oscillator to be
gturned off and the processor to "sleep" until an external
interrupt (mc:i), Port B interru P T+mer interrupt (if using
an external timer clock), or RE E occurs.
• WAIT - The WAIT instruction causes all processor
clocks to stop, but leaves the Timer and SPI clocks run-
ning. This "rest" state of the processor can be cleared by
reset, an external interrupt (mc:i), Timer interrupt, SPI
Interrupt, or Port B interrupt. There are no special wait
vectors for these individual interrupts.
Software Interrupt (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware
interrupts. The SWI is executed regardless of the state of
the interrupt mask (I bit) in thec0ndition code register. The
interrupt service routine address is specified by the con-
tents of memory location $1 FFC and $1 FFD.
External Interrupt
Ifthe interrupt mask (I bit) ofthecondition code register has
been cleared and the external interrupt pin (iRO) has gone
low, then the external interrupt is recognized. When the
interrupt is recognized, the current state of the CPU is
pushed onto the stack and the I bit is set. This masks further
interrupts until the present one is serviced. The interrupt
service routine address is specified by the content of memo-
ry location $1 FFA and $1 FFB. Either a level-sensitive and
negative edge-sensitive trigger, or a negative edge-sensi-
tive only trigger are available as a mask option. Fig. 11
shows both a functional and mode timing diagram for the
interrupt line. The timing dia9!!!!l shows two different
treatments of the interrupt line (lRQ) to the processor. The
first method shows single pulses on the interrupt line
______________________________________________________________ 203
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