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PDF CDP1804AC Data sheet ( Hoja de datos )
| Número de pieza | CDP1804AC | |
| Descripción | CMOS 8-Bit Microprocessor | |
| Fabricantes | GE | |
| Logotipo |  |
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1800-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1804AC
TERMINAL ASSIGNMENT
CLOCI(
WATt
cern
SCI
SCO
MRo
BUS 7
BUS 6
aus 5
BUS 4
BUS 3
BUS 2
BUS I
BUS 0
EMS/ME
N2
NI
NO
VSS
.0
39
38
37
36
35
3.
33
32
10 31
" 30
12 29
13 20
I. 27
15 2.
"I.
17 2.
I. 23
19 22
20 21
TOP VIEW
=Voo
l5MATN
l5iiAOij'f
INTERRUPT
l<iV/li
TPA
TPO
MA7
MA.
MA5
MA.
MA3
MA2
MAl
mMmAO
m
En
92CS~ 34980
CMOS a-Bit Microcomputer With
On-Chip RAM, ROM, and Counter/Timer
Performance Features:
• Instruction time of 3.2 p.s, -40 to +850 C
• 123 instructions-upwards sofware compatible with
CDP1802, CDPI805A, and CDP1806A
• BCD arithmetic instructions
• Low-power IDLE mode
• Pin compatible with CDP1802, CDPI805A, and CDP1806A
except for terminal 16 (terminal 18 for chip-carrier package)
• 64K-byte memory address capability • 16 x 16 matrix of on-board registers
• 2 K bytes of on-chip ROM
• On-chip crystal or RC control/ed oscillator
• 64 bytes of on-chip RAM
• 8-bit Counter/Timer
The RCA-CDP1804AC is a functional and performance
enhancement of the CDP1802, CDP1805A, and
CDP1806A CMOS 8-bit register-oriented microprocessor
series and is designed for use in a wide variety of general-
purpose applications.
The CDP1804AC hardware enhancements include a 2K-
byte ROM, a 64-byte RAM, and a 8-bit presettable down
counter. The Counter/Timer, which generates an internal
interrupt request, can be programmed for use in time-
base, event-counting, and pulse-duration measurement
applications. The Counter/Timer underflow output can
also be directed to the 0 output terminal.
The CDP1805AC and CDP1806AC which are identical to
the CDP1804AC, except for the on-chip memory, should
be used for CDP1804AC development purposes.
The CDP1804AC software enhancements include 32 more
instructions than the CDP1802. The 32 additional
software instructions include subroutine call and return
capability, enhanced data transfer manipulation,
counter/timer control, improved interrupt handling,
single-instruction loop counting, and BCD arithmetic.
Upwards software and hardware compatibility are
maintained when substituting a CDP1804AC for other
CDP1800-series microprocessors. Pinout is identical
except for the replacement of Vee with EMS/ME.
The CDP1804AC has an operating voltage range of 4 V to
6.5 V and is supplied in a 40-lead hermetic dual-in-line
ceramic package (D suffix), in a 40-lead dual-in-line
plastic package (E suffix), and in a 44-lead plastic chip-
carrier package (0 suffix).
-- - - - ir-r~~~~~~==== "AtiDRfsSBUrS- -- ----- -- -- ---- -- I-II
~ ~ ,17
COPl851
PIO
CONTROL
CDPI804AC
8-BITCPU
WITH ROM,
~~~Nf~~,
MWR
TPA
1-
MA~MA71
I
rM~MA7_,
1I
II 1
---~MRD
1-----+lMRD
1
r----1___ J ROM I
1_
MWR
II
---~TPA
:
iI RAM
TIMER
I IOUT
CEO"-----+1cs
d""--I
- - -.,cs
I
- i T1 BUSO-BUS7
1_ I
-~CL!Sl~O-BU.!!...JI
r-,
J ~ : :~::::----- _____ ~ _________ ..J 1
' -_ _ _ _ _ _--=:.....:::..:...:=:....::::.::...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..J 92CM-34~1
"-OPTIONAL EXPANSION MEMORY-----.I
Fig. 1 - Typical CDP1804AC microprocessor system.
File Number 1371
60 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
1 page  
1800-88rle. Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1804AC
TIMING WAVEFORMS FOR POSSIBLE OPERATING MODES
M1P--------------~,-------------~
* ;W --------------,ILLJr----------L-j
DATA BUS ..,,1I!'7V~7A~7L~I7D:~7~:/_A:;;:Fs/R_O:;M"~.M:;E;M~7~O7R~7Y~~;;:/:;;:;/::I"F==jlv:;h/_:;,,/:;'7~-r---:::V.:-::LlD~D;:-;.t=.-;:-::::::-:::cPIJ::---,,-;12
·NOTE FOR RUN (RAM ONLY) MODE:
i l i HAS A MINIMUM SETUP AND HOLD TIME WITH RESPECT TO THE
BEGINNINQ Of CLOCK 10. FOR A MI!MORY READ OPERAnON, RAM DATA
WILL APPEAR ON THE DATA BUS DURING THE TIMEili 18 ACTIVE AFTER
CLOCK 31. THE TIME SHOWN CAN BE LONGER, IF FOR INSTANCE, A DMA
OUTOPERAnON 18 PERFORMED ON INTERNAL RAM DATA,TOALLOW OATA
ENOUGH TIME TO BE LATCHED INTO AN EXTERNAL DEVICE. THE INTERNAL
RAM IS AUTOMATICALLY DE8ELECTED AT THE END OF CLOCK 71,
INDEPENDENT OFiii.
NOTE FOR RUN (ROM/RAM) MODE:
INTERNAL MEMORY DATA WILL APPEAR ON THE DATA BUS AFTER CLOCK
PULSE 31.
Fig. 3 -Internal memory operation timing waveforms for CDP1804AC.
CLOCK
:~~~lT~P:;BI:H;'G;";.;YT;E~I~:::;L"';;.;YT;E::JL~I:H~'G:H~.~YT;E~I~::::LCNV:::.Y:rTE-::L--:.:-:
MRD-----,l_ _ _ _ _ _ _~Jr-----------
M1P------------------+--------------~
* -EMS
OUT
DATA aus
~
DATA LATCHED IN CPU
'--_ _ _.....r
VALID OATA FROM CPU
·'OR RUN (ROM/RAM) MODE ONLY.
NOTE: FOR THE RUN (RAM ONLY) MODE 'II! MUST BE HIGH DURING
EXTERNAL MEMORY ACCESSES.
92CS-34984
Fig. 4 - External memory operation timing waveforms for CDP1804AC.
SIGNAL DESCRIPTIONS
BUI 0 to BUS 7 (Data Bu.):
8-blt bidirectional DATA BUS lines. These lines are used
for transferring data between the memory, the
microprocessor, and I/O devices.
NO to N2 (I/O) Lin••):
Activated by an I/O instruction to signal the 1/0 control
logic of a data transfer between memory and I/O
interface. These lines can be used to issue command
codes or device selection codes to the I/O devices. The N
bits are low at all times except when an I/O instruction Is
being executed. During this time their state is the same as
the corresponding bits in the N register. The direction of
data flow is defined in the I/O instruction by bit N3
(internally) and is indicated by the level of the MRD
signal:
MRD = Voo: Input data from I/O to CPU and Memory
MRD = Vss: _Output data from Memory to I/O
64 _______________________________________________________
5 Page 
1BOO-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1804AC
COPI804AC
Rp The Fie time constant
should be greater
than the oscillator
start-up time
(tYPically 20 ms)
92CS-3809B
Fig. 11 - Reset/Run (RAM only) diagram.
PAUSE
Pause is a low power mode which stops the internal CPU
timing generator and freezes the state of the processor.
The CPU may be held in the Pause mode indefinitely.
Hardware pause can occur at two points in a machine
cycle, on the low to high transition of either TPA or TPB.
A TPB pause can also be initiated by software with the
execution of an IDLE instruction. In the pause mode, the
oscillator continues to run but subsequent clock
transitions are ignored. TPA and TPB remain at their
previous state (see Fig. 12).
Pause is entered from RUN (RAM only) by dropping
WAIT low, and from RUN (ROM/RAM) by raising CIJ:AR
high. Appropriate setup and hold times must be met.
If Pause is entered while in the event counter mode, the
appropriate Flag transition will continue to decrement the
counter.
Hardware-initiated pause is exited to RUN (RAM only) by
raising the waTiline, and the RUN (ROM/RAM) by
lowering CLEAR. Pause entered with an IDLE instruction
requires riMA, INTERRUPT or RESET to resume
execution.
TPA PAUSE TIMING
RUN
May be initiated from the Pause or Reset mode functions.
If initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the
next high-to-Iow clock transition, while if paused at TPB,.
it will resume on the next low-to-high clock transition.
(See Fig. 12). When initiated from the Reset operation, the
first machine cycle following Reset is always the
initialization cycle. The initialization cycle is then
followed by a DMA (S2) cycle or fetch (SO) from location
0000 in memory.
SCHMITT TRIGGER INPUTS
All inputs except BUS 0 - BUS 7 and ME contain a
Schmitt Trigger circuit, which is especially useful on the
CLEAR input as a power-up RESET (See Fig. 10 and 11)
and the CLOCK input (See Fig. 7 and 8).
STATE TRANSITIONS
The CDP1804AC state transitions are shown in Fig. 13.
Each machine cycle requires the same period of time, 8
clock pulses, except the initialization cycle (INT) which
requires 9 clock pulses. Reset is asynchronous and can
be forced at any time.
RESET
CLOCK
TPA
00 01
PAUSE
r- II rl~1-t'--+-.
IpLH--j
II
't~tliI I
~ I--tsu
TPB PAUSE TIMING ENTER RESUME
PAUSE
RUN
PRIORITY:
RESET
EQ!!CE so, $1
DMA IN
~AOUT
INT·DiiA
12CS·34778A1
Fig. 13 - State transition diagram.
CLO* C+ K~~
pI I II
i ~TPB tPLH--i
'\:-tPHL
I I I '------
II
II
I
92CM w 31944RI
NOTE:
tsu tH
1.- tsu
I
PAUSE (IN CLOCK WAVEFORM) WHILE REPRESENTED HERE AS ONE
CLOCK CYCLE IN DURATION, COULD BE INFINITELY LONG.
Fig. 12 - Pause mode timing waveforms.
70 ____________________________________________________________
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CDP1804AC.PDF ] | |
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