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PDF CDP1802A Data sheet ( Hoja de datos )
| Número de pieza | CDP1802A | |
| Descripción | CMOS 8-Bit Microprocessor | |
| Fabricantes | GE | |
| Logotipo |  |
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________________ 1800-Serle. Mlcroproce.sors and Microcomputers
CDP1802A, CDP1802AC
CLOCK
WiTt
ctm
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.co
111m
IUS 1
IUS.
BUS •
IUS 4
IUS 3
IUS 2
..IUS I
auso
,Yee
NO
Yss
·0,
·•
'0
"12
.."",.
.,17
oo
20
..,. .........0 Yoo
1TIl
.....'"""'"HiT!IIIfilI'f
.."-."...m..........."".,......,.,
m
TOP .,I£W
TERMINAL ASSIGNMENT
CMOS 8-Bit Microprocessor
Features:
• Minimum instruction fetch-execute time of 5 IlS or 7.5 IlS at VDD = 5 V;
2.51ls or 3.75 IlS at VDD = 10 V
• Any combination of standard RAM and ROM up to 65,536 bytes
• Operates with slow memOfles, up to 1 IlS access time at fCL = 4 MHz
• 8-bit parallel organization with bidirectional data bus and multiplexed
addresS bus
• 16 x 16 matrix of registers for use as multiple program counters,
data pointers, or data registers
• On-chip DMA, mterrupt, and flag inputs
• Programmable smgle-bit output port
• 91 easy-to-use instructions
The RCA-CDP1802A LSI CMOS 8-blt register-oriented
central-processing unit (CPU) is designed for use as a
general-purpose computing or control element in a wide
range of stored-program systems or products.
The CDP1802A includes all of the circuits required for
fetching, interpreting, and executing Instructions which
have been stored in standard types of memories. ExtenSive
input/output (1/0) control features are also provided to
facilitate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a syn-
chronous interface to memories and external controllers
for 1/0 devices, and minimizes the cost of interface con-
trollers. Further, the 1/0 interface is capable of supporting
devices operating in polled, interrupt-driven, or direct
memory-access modes.
The CDP1802A and CDP1802AC are functionally identical.
They differ in that the CDP1802A has a recommended
operating voltage range of 4 to 10.5 volts, and the
CDP1802AC a recommended operating voltage range of 4
to 6.5 volts.
These types are supplied in 40-lead dual-in-line side-
brazed ceramiC packages (D suffix). 40-lead dual-In-Iine
plastic packages (E suffix) and 44-lead plastic chip-carrier
(PCC) package (0 suffix). The CDP1802AC isalso available
in chip form (H suffix).
~
<==
CDPI852
INPUT PORT CS2
Ir
MAO-7
NO
DATA CSt
~:
MRD
CDPI802
8-BIT CPU
-~DATA CST
CDPI852 CS2
OUTPUT PORT
CLOCK
I-- NI
I-- TPB
DATA
iiiiR
TPA
II
ADDRESS BUS
\7
MAO-7
MirD
CDPI833
I K-ROM
CEO
TPA
DATA
V
-BI' DATA BUS
Fig. 1 - Typical CDPlli02A small microprocessor system.
\}
MAO-4
MRD
COPI824
32 BYTE RAM
IiWii
CS
DATA
II
92CM- S4.SIRt
File Number 1305
_____________________________________________________________ 17
1 page  
________________ 1800-Serle8 Microprocessors and Microcomputers
CDP1802A, CDP1802AC
CONTROL AND
TIMING lOGIC
Fig 8 - CDP1B02A block diagram.
N0}oX/O
NI MMANDS
NZ
BUS
BUS 5
Bun
BUS
ClOClC
ADDRESS~~~H~I~BY~T~E~_L_ _ _ _ _ _~L~OW~~~T~E~_ _ _ _ _ __L~H~I~8~Y~TE~_L_ _ _ _ _ _~LOW~~8Y~TE~_ _ _ _ _ __ L_ _
TPA -----1IL..-.________--In......._________
________________T~ _________________~r-1~
~r_1L....
'--_..r. -
Fig. 9 - BasIc de timing waveforms, one instruction cycle.
21
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
TABLE I - INSTRUCTION SUMMARY (Conl'd)
INSTRUCTION
MNEMONIC
BRANCH INSTRUCTIONS-SHORT BRANCH
SHORT BRANCH IF EF4=1
(EF4=VSS)
SHORT BRANCH IF EF4=0
( EF4=VCC)
B4
BN4
BRANCH INSTRUCTIONS-LONG BRANCH
LONG BRANCH
LBR
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF D=O
NLBR
LBZ
LONG BRANCH IF D NOT 0
LBNZ
LONG BRANCH IF DF=1
LBOF
LONG BRANCH IF DF=O
LBNF
LONG BRANCH IF 0=1
LBO
LONG BRANCH IF 0=0
LBNO
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF D=O
LONG SKIP IF 0 NOT 0
LONG SKIP IF OF=1
LONG SKIP IF OF=O
LONG SKIP IF 0=1
LONG SKIP IF 0=0
LONG SKIP IF IE=1
SKP
LSKP
LSZ
LSNZ
LSDF
LSNF
LSO
LSNO
LSIE
OP
CODE
OPERATION
37 IF EF4=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
3F IF EF4=O, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
CO M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ca§ R(P)+2-R(P)
C2 IF 0=0, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
CA IF 0 NOT 0, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
C3 IF OF=1, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
CB IF OF=O, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
C1 IF 0=1, M(R(P))-R(P).1
M(R(P)+1 )-R(R).O
ELSE R(P)+2-R(P)
C9 IF 0=0, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
3a§ R(P)+1-R(P)
ca§ R(P)+2-R(P)
CE IF 0=0, R(P)+2-R(P)
ELSE CONTINUE
C6 IF D NOT 0, R(P)+2-R(P)
ELSE CONTINUE
CF IF OF=1, R(P)+2-R(P)
ELSE CONTINUE
C7 IF OF=O, R(P)+2-R(P)
ELSE CONTINUE
CO IF 0=1, R(P)+2-R(P)
ELSE CONTINUE
C5 IF 0=0, R(P)+2-R(P)
ELSE CONTINUE
CC IF IE=1, R(P)+2-R(P)
ELSE CONTINUE
__________________________________________________________________ 27
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CDP1802A.PDF ] | |
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