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PDF FM8P59 Data sheet ( Hoja de datos )
| Número de pieza | FM8P59 | |
| Descripción | EPROM/ROM-Based 8-Bit Microcontroller | |
| Fabricantes | Feeling Technology | |
| Logotipo |  |
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FEELING
TECHNOLOGY
FM8P59
EPROM/ROM-Based 8-Bit Microcontroller
Devices Included in this Data Sheet:
‧ FM8P59AE : 28-pin EPROM device
‧ FM8P59BE : 32-pin EPROM device
‧ FM8P59A : 28-pin Mask ROM device
‧ FM8P59B : 32-pin Mask ROM device
FEATURES
‧ Only 47 single word instructions
‧ All instructions are single cycle except for program branches which are two-cycle
‧ 13-bit wide instructions
‧ All ROM/EPROM area GOTO/FGOTO instruction
‧ All ROM/EPROM area subroutine CALL/FCALL instruction
‧ 8-bit wide data path
‧ 5-level deep hardware stack
‧ 4K x 13 bits on chip EPROM/ROM
‧ 144 x 8 bits on chip general purpose registers (SRAM)
‧ Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
‧ Direct, indirect addressing modes for data accessing
‧ 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
‧ Internal Power-on Reset (POR)
‧ Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
‧ Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
‧ On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
‧ Three I/O ports IOA, IOB and IOC with independent direction control
‧ 16 soft-ware control pull-high pins: Port B/Port C
‧ 8 soft-ware control pull-down pins:IOA0~A3/IOB0~B3
‧ 2 soft-ware control open-drain pins: IOC6/IOC7
‧ One internal interrupt source: Timer0 overflow; Two external interrupt source: INT0 pin, INT1 pin
‧ Wake-up from SLEEP by Port B/IOC4/IOC5 input falling
‧ Power saving SLEEP mode
‧ Programmable Code Protection
‧ Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- XT: Crystal/Resonator Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
‧ Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev0.99 Jul 20, 2005
P.1/FM8P59
1 page  
FEELING
TECHNOLOGY
FM8P59
1.0 MEMORY ORGANIZATION
FM8P59 series memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8P59 series have an 12-bit Program Counter capable of addressing a 4K×13 program memory space.
The RESET vector for the FM8P59 series is at FFFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8P59 series has program memory size greater than 1K words, but the CALL and GOTO instructions only have a
10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow
CALL and GOTO instructions to address the entire 4K program memory address range for FM8P59 series, there is
another two bits to specify the program memory page. This paging bit comes from the PCHBUF<3:2> bits. When
doing a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<3:2> are programmed so that the
desired program memory page is addressed. When one of the return instructions is executed, the entire 12-bit PC is
POPed from the stack. Therefore, manipulation of the PCHBUF <3:2> is not required for the return instructions.
User can use “PAGE” instruction to change memory page and maintains the program memory page. Otherwise,
user can use “FCALL(far call)/FGOTO(far goto)” instructions to program user's code.
FIGURE 1.1: Program Memory Map and STACK
PC<11:0>
FFFh
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8P59 Series
Rev0.99 Jul 20, 2005
P.5/FM8P59
5 Page 
FEELING
TECHNOLOGY
FM8P59
Situation 5: RETIA, RETFIE, or RETURN Instruction
PCH
11 10 9 8 7
PC
PCL
0
STACK<11:0>
----
PCHBUF
Situation 6: Instruction with PCL as destination (except TBL instruction)
PCH
11 10 9 8 7
PC
PCL
PCHBUF<3:0>
0
----
PCHBUF
ALU result<7:0>
or Opcode<7:0>
Situation 7: TBL Instruction
PCH
11 10 9 8 7
PC
PCHBUF<3:2>
PCL
----
PCHBUF
0
ALU result<7:0>
PCH<9:8> bits are unchanged
Note: PCHBUF is used for instruction with PCL as destination, GOTO and CALL instructions.
Rev0.99 Jul 20, 2005
P.11/FM8P59
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FM8P59.PDF ] | |
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