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PDF TC518129AFWI-10 Data sheet ( Hoja de datos )

Número de pieza TC518129AFWI-10
Descripción SILICON GATE CMOS PSEUDO STATIC RAM
Fabricantes Toshiba 
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No Preview Available ! TC518129AFWI-10 Hoja de datos, Descripción, Manual

TOSHIBA
1l:518129~-10
SILICON GATE CMOS
131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518129AFWI is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129AFWI
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518129AFWI operates from a single 5V power supply. Refreshing is supported by a refresh (RFSHl input which
enables two types of refreshing - auto refresh and self refresh. The TC518129AFWI features a static RAM-like interface with a write
cycle in which the input data is written into the memory cell at the rising edge of R!W thus simplifying the microprocessor interface.
A CS standby mode interface is incorporated in the TC518129AFWI, with the CE2 pin in the TC518128A family changed to a CS
pin. The TC518129AFWI is guaranteed over an operating temperature range of -40 - 85°C so the TC518129AFWI is suitable for use
in wide operating temperature systems. It is available in a 32-pin, 0.525 inch small outline plastic flat package.
Features
• Organization: 131,072 words x 8 bits
• Single 5V power supply
• Fast access time
tCEA CE Access Time
100ns
tOEA OE Access Time
40ns
tRC Cycle Time
160ns
Power Dissipation
330mW
Self Refresh Current
200~
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Wide operating temperature:
-40 - 85°C
• Inputs and outputs TIL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Package
- TC518129AFWI: SOP32-P-525
Pin Connection
iffiH
A16
A14
A12
A7
A6
AS
A4
A3
A2
A1
AO
001
002
003
GNO
x~~
CS
RJW
A13
A8
A9
All
Ol
AlO
CE
1108
007
006
1105
1104
Pin Names
AO ~ A16
RlW
DE
RFSH
CE
CS
1/01 ~ 1/08
VDD
GND
Address Inputs
ReadIWrite Control Input
Output Enable Input
Refresh Input
Chip Enable Input
Chip Select Input
Data Inputs/Outputs
Power
Ground
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0-115

1 page




TC518129AFWI-10 pdf
Static RAM
TC518129AFWI-10
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 and 100F4 depend on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100J.1S with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tr = 5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H = 2.6V
V1L = 0.6V
INPUT
2.6V
O.6V
V1H = 2.4V
V1L = 0.8V OUTPUT
VOH = 2.2V
VOL =0.8V
INPUT REFERENCE
lEVEL
.v
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 2 TIL loads and 100pF.
9) tcHz, toHZ, tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data in latched at the earlier of RNV or CE rising edge. Therefore, the input data must
be valid during the setup time (tosw or tosd and hold time (tOHW or tOHd.
11) All address inputs are latched at the falling edge of CE. Therefore, all the address inputs must be valid during 1Asc and tAHc.
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE = V1H.
Auto refresh : RFSH pulse width:S tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The timing parameter tFRS must be met for proper device operation under the following conditions:
• after self refresh
• if RFSH = "L" after power-up
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
D-119

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