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Numéro de référence | TC58DVM92A5TA00 | ||
Description | 512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | ||
Fabricant | Toshiba | ||
Logo | |||
1 Page
TC58DVM92A5TA00
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The device is a single 3.3 V 512Mbit (553,648,128 bit) NAND Electrically Erasable and Programmable Read-Only
Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell allay 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
• Mode control
Serial input/output
Command control
• Power supply
VCC = 2.7 V to 3.6 V
• Access time
Cell array to register 25 μs max
Serial Read Cycle 40 ns min
• Program/Erase time
Auto Page Program 300 μs/page typ.
Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (40 ns cycle)
Program (avg.)
Erase (avg.)
Standby
20 mA max.
20 mA max.
20 mA max.
50 μA max
• Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
1 2010-07-13
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Pages | Pages 30 | ||
Télécharger | [ TC58DVM92A5TA00 ] |
No | Description détaillée | Fabricant |
TC58DVM92A5TA00 | 512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | Toshiba |
US18650VTC5A | Lithium-Ion Battery | Sony |
TSPC106 | PCI Bus Bridge Memory Controller | ATMEL |
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