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CD4555BMS fiches techniques PDF

Intersil Corporation - CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers

Numéro de référence CD4555BMS
Description CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CD4555BMS fiche technique
December 1992
CD4555BMS
CD4556BMS
CMOS Dual Binary to 1 of 4
Decoder/Demultiplexers
Features
• High Voltage Type (20V Rating)
• CD4555BMS: Outputs High on Select
• CD4556BMS: Outputs Low on Select
• Expandable with Multiple Packages
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Decoding
• Code Conversion
• Demultiplexing (Using Enable Input as a Data Input
• Memory Chip-Enable Selection
• Function Selection
Description
CD4555BMS and CD4556BMS are dual one-of-four decod-
ers/demultiplexers. Each decoder has two select inputs (A
and B), an Enable input (E), and four mutually exclusive out-
puts. On the CD4555BMS the outputs are high on select; on
the CD4556BMS the outputs are low on select.
When the Enable input is high, the outputs of the
CD4555BMS remain low and the outputs of the
CD4556BMS remain high regardless of the state of the
select inputs A and B. The CD4555BMS and CD4556BMS
are similar to types MC14555 and MC14556, respectively.
The CD4555BMS and CD4556BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4555B Only
*H46 †H4T
H1E
H6W
†CD4556B Only
Pinouts
CD4556BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
CD4555BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
Functional Diagrams
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
VSS 8
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
CD4555BMS
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
VSS 8
CD4556BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1249
File Number 3346

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